Logic Design for Array-Based Circuits

by Donnamaie E. White

Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc.

 

The original form of this book was published by Academic Press, 1250 Sixth Avenue, San Diego, California 92101-4311 in 1992. ISBN 0-12-746660-6. The figures were reproduced with the permission of Applied Micro Circuit Corporation. The Q20000 Series and other bopolar and BiCMOS series referenced belong to AMCC. Note that this book is dated as to the AMCC ASIC business. It represents design flow from the late 1980's to early 1990's. Thge design flow bears a remarkable similarity to the current design flow used by Cadence and Synopsys - with the switch from schematic capture to HDL code (Verilog, RTL) , synthesis (Design Compiler), timing analysis (PrimeTime) and Place & Route (the old Gate Ensemble to today's programs from Synopsys, Cadence, and others), and with more of the validation steps now performed by various software programs. A basic understanding of the underlying methodology to what we do today with deep submicron technologies is still a good read. Everything that bipolar design had to handle in the early 1980's is what we now must handle for 0.25 micron and belowCMOS technologies.

This book was based on classes taught at USCD and at AMCC's customer Design Centerin the late 1980-early 1990s.

Customer training courses prepared by high-technology vendors are a required extension to that training available in the engineering classes at the college level. The quality of that training can vary with the experience of the instructor. The experience of the instructor with the nuances of the products is one facet. The teaching expertise is another. By providing this supplement, it would be possible for other, less experienced instructors, to take over the actual presentation of the seminars while ensuring no loss of insight into the methodology or product taught.


Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc.
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