Logic Design for Array-Based Circuits

by Donnamaie E. White

Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc.



The voltage supplies are +5V and GND; for use with TTL I/O in a mixed I/O mode design.

ECL Emitter-coupled logic
A differential switch-based logic family using parallel transistors and series switches. ECL is extremely high-speed. The normal power supply is -5.2V for ECL 10K and -4.5V for ECL 100K. Logical one is -0.8V; logical zero is -1.80V for -5.2V ECL 10K (an average voltage magnitude of 1.3V). The speed comes from the fact that the transistors within the gates are never driven into saturation, eliminating the time required for the transistors to come out of saturation.

See ECL.

ECL 100K
ECL normally using a power supply of -4.5V; it is temperature- compensated.

ECL, pseudo
This is +5V REF ECL, either ECL 10K or ECL 100K operated with a TTL power supply of +5V, to allow ECL functions on a TTL board.

Electronic design interface format which AMCC will use to replace AGIF. This is a proposed standard (one of several). EDIF can already be used to transfer a Verilog HDL design to Mentor schematics.

A circuit used to provide drive after the logic portion of an ECL circuit; the voltage gain of an emitter-follower is close to unity.

Equivalent gates
A sizing methodology for gate arrays. There is no standard method of determining equivalent gate counts. This should not be used to "size" a circuit design.

Engineering Rules Checks or engineering reports and checks. Support software on the various EWS designed to flag miss-connects (missed connections), naming errors, improper wire-ORs, excessive fan-out, GND checks, etc., and to generate reports on macro usage, current dissipation and loading.

Engineering workstation; A computer-graphics system specifically oriented to support circuit design development from schematic capture through simulation, timing analysis, testability analysis, and eventually test pattern generation. Some can handle layout, PG tape pattern generation. At the minimum, it will produce a netlist from the captured schematic. Adding a framework allows easier use of 3rd party software and provides better support for the entire design process.

External hold time
The time that data on an external package pin must be held stable after the arrival of the active edge of the clock at a second external package pin.

External package pin
A package pin, usually carrying a signal. See package signal pin.

External pin
A pin on the outside on the die used to interface the circuitry to the outside world.

External set-up time
The time that data on an external package pin must be stable before the active edge of the clock arriving at a second external package pin.


Falling-edge active
A flip/flop or latch which can change state during the falling edge of the active clock and remains static during the rising edge of the active clock.

The number of electrical loads presented by an input pin to the driving device, applies to macros within an array or to discrete devices.

The number of components to which a signal is connected.

Fault, as in logical fault
An error due to hard or soft failure such that the logical function implemented is not what is desired. (E.g., SA1, SA0, SAX)

Fault coverage
The inclusion in the test set of a test to cover each possible, observable fault at least once. A measure of this coverage expressed in per cent. Recommended coverage is 90% or higher.

Fault grading
The process of estimating the percentage of faults tested by the test vectors. Fault grade software is available on the workstations and some simulator systems, but modeling differences make comparisons of fault grade scores difficult.

Fixed ground
An array pad designated for use as a ground pad and not capable of being used for any other purpose. Usually, an array fixed ground pad must be bonded to the package to an internal ground plane or to a package pin.

Fixed power
An array pad designated for use as a power pad and not capable of being used for any other purpose. Usually, an array fixed power pad must be bonded to the package to an internal power plane or to a package pin.

A minimum volume package with leads or connectors distributed radially on all four sides and paralleled with the die cavity. Flat packs are commonly used where a high pin-count, very light weight packaging system is needed. Used in military and space systems.

Fan-Out Derating A net parameter (AMCC software) that specifies the percentage derating to be applied to the driving macro pin fan-out load limit.

A Front-Annotation data file where xxx[x] defines the product_grade and power_supply, and ews defines the simulator or workstation for which the file has been formatted.

Abbreviation for flat pack. Package type.

Field programmable gate array.

Field programmable logic array; "AND" array user-programmable, some pre-selected subset of the 2**n product terms is available from the n inputs (array-dependent), "OR" array user-programmable, any product term (of those available) and be ORed to the y outputs.

Field programmable logic sequencer.

The method used to predict the loading on the internal net of a circuit by using the actual fan-out (electrical) load, the actual wire-OR (electrical) load, an averaged package pin capacitance, and the statis-tically estimated metal (physical) load. The estimate is the mean of the collected data of observations made on previous circuits. The estimate is a function of the fan-out and wire-OR loads, in terms of the physical pin con-nect and the array (die size). Output nets use actual system load capa-citance and estimated package pin capacitance as the basis for time delays.

Full custom ICs
All devices and components are designed specifically for the application. This approach takes the most design time, the most debug time, and is the most expensive. Saving in die size are not achievable unless the designer is very experienced. It is the most difficult approach. See Silicon compiler.

Function cell
Internal logic cell capable of supporting one or more logic operations, depending on the cell size.

Function macro
Internal macro, on bipolar arrays, operates at internal ECL levels (one-half volt ECL for AMCC bipolar arrays), placed on internal logic or buffer cell (optional placement). Operates at CMOS levels inside BiCMOS arrays.

Functional elements
See function macro.

Functional simulation
Simulation designed to examine the functional integrity of a circuit design.

Degree of density of a design; also the logical integrity of a Boolean circuit, independent of detailed speed or parametric behavior.

Fuse-programmable devices
Example devices are PROMs, PLAs, and PALs.


1. Physical input to a CMOS transistor pair.
2. A logic gate such a NOR or NAND.
3. A number of repetitive active element groups.
4. A transistor.

Gate array
An array formed from elementary gates, usually 2-input NOR or 2-input NAND (CMOS) gates. A gate array is configured into a variety of logical circuits through customized interconnect. A gate array is often defined as a semicustom digital integrated circuit.

Gate delay
The time it takes to propagate a signal through a gate. Gate equivalent circuit Unit of measure.
Equivalent gates refers to the number of gates of a given complexity (2-input NOR, 2-input NAND) that would be required to perform the same function.

A net parameter (AMCC software) that is attached to the output signal for the parametric gate tree.


Hardware Description Language from the IEEE Standards Subcommittee (IEEE SC20 ATPG).

Hierarchical structuring
Generally a tree-like structure for top-down design from block diagram to detailed circuit. Depending on the EWS, this can involve nesting, blocks, cells (on-page-nest) and multiple directory levels.

Hertz; HZ

High performance
High-speed, high density, it may also mean high-power.

High speed macro option
This version of the macro is designed for high speed applications with associated greater power dissipation.


I cell
Accommodate macros for input type functions only. CMOS refers to these as dedicated input cells.

Integrated circuit

Integrated injection logic.

I/O cell Stands for Input/Output Cell
An Interface cell that accommodates macros for input, output and bidirectional functions as well as 3-state enable drivers; where interface functions are performed.

Interconnect verification
Validation of the interconnections between macros used to form a circuit.

Taken to be the transition between external and internal levels of a device.

Interface cell utilization limit
The percentage of interface cells that may be used. This limits has application for specific arrays that have a non-one to one ratio to pads. In most cases 100% interface cell utilization is an assumed limit.

Interface macro
A macro whose function is to perform the translation between external and internal device levels.

Internal cell utilization
See cell utilization. A guideline for the percentage of internal cells that may be used before routing becomes difficult or impossible.

Internal logic cell
Cells designed for logical functions and not for I/O; can accommodate certain buffers.

Internal logic macro library
A set of macros that may be placed on the internal logic cells; they may or may not be restricted to those cells.

Internal macro
Internal logic macro; A functional macro.

Internal pin
A pin on a macro that is used to connect it to the other macros on the array (in the circuit). Internal pin count is a measure of routability.


Early low-density technology.

Junction temperature
See TJ. The temperature internal to the transistors on the array.


Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc.
For problems or questions on these pages, contact donnamaie@-no-spam-sbcglobal.net