Logic Design for Array-Based Circuits - D. E. White - eBook


Logic Design for Array-Based Circuits by Donnamaie E. White Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc.

Table of Contents Preface Overview Chapter 1 Introduction Chapter 2 Structured Design Methodology Chapter 3 Sizing the Design Chapter 3 Appendix = Case Study in Sizing a Design Chapter 4 Design Optimization Chapter 5 Timing Analysis for Arrays Chapter 6 External Set-up and Hold Times Chapter 7 Power Considerations Case Study: DC Power Computation Case Study: AC Power Computation Chapter 8 Simulation Introduction Simulators - The Tools Non-Native Simulators AMCC's Race Check Timing Verifiers Hardware Emulators Golden Simulators Design Validation Wafer Sort/Packages Part Sort Functional Simulation Fault-Grading Testability Analysis Simulation Rules At-Speed Simulation for Timing Verification AC Tests Parametric Vectors Gate Tree - Any Circuit Hazards Structural Hazard Types Functional Hazards What is Required to Fix Race Problems Exercises Case Study: Simulation Introduction The Schematic Output Enable Clock MUX Enable Design Checks Annotation The Simulations Functional Simulation Parametric Simulation At-Speed Simulation AC Test Exercises Chapter 9 Faults and Fault Detection Chapter 10 Design Submission ASIC Glossary Glossary A-D Glossary E-K Glossary L-R Glossary S-Z Symbols	Simulation Last Edit July 22, 2001 At-Speed Simulation There are no coverage rules for an at-speed analysis. It can be done using a timing verifier or a simulator. The output format is vendor-specific and in this case matches all other simulations performed for the circuit. The at-speed simulation is to be run at the specified maximum operating frequency of the circuit. The actual maximum frequency of this circuit is left as a class exercise. Two simulations are shown - Figure 8-4 shows the maximum worst-case sampled simulation and Figure 8-5 shows the maximum worst-case print on change. Sampling depends on the maximum frequency. The print on change file has an entry for each time that a monitored signal changes state. (This version of the circuit had 3-state outputs.) Figure 8-4a At-Speed Sampled Simulation - 32-Bit Register (partial) Figure 8-4b At-Speed Sampled Simulation - 32-Bit Register - Full listing Figure 8-5a At-Speed Print-On Change Simulation - 32-Bit Register (partial) Figure 8-5b At-Speed Print-On-Change Simulation - 32-Bit Register - Full listing Note that there are no switching restrictions for outputs in a vector for this simulation, which considerably reduces the size of the sampled vector output file in comparison to that for the functional simulation. The at-speed simulation is never run on a tester. The reset is handled as before. Exercise Create a complete at-speed vector set for the schematics shown in the Appendix of Chapter 3 (no 3-state outputs).
Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc. For problems or questions on these pages, contact [email protected]