Logic Design for Array-Based Circuits
Sizing the Design - Selecting the Array
Functional Specification - A Closer Look
The functional or target specification is the first level of description of the project that may encompass one or more arrays when the design is partitioned. There may be a specification tree with the total project at the top node and individual circuit blocks or modules detailed underneath. Topics included in a functional specification are listed in Table 3-1.
At this early stage, a functional description of what is to be accomplished is created along with some of the top-level circuit requirements.
For the partitioned project (multiple arrays), the individual array specifications would include a description of array interfacing.
Interconnection between arrays is faster when done with ECL. When choosing single or dual (differential) rail ECL use the following guidelines:
The potential need for differential ECL should be indicated at the functional specifica tion level.
It is also a good guideline for how to break up a 6-8 milllion gate array into top-level blocks - keep the critical paths inside the block if possible. Interblock connections today are what interarray connections were yesterday.
In today's very large designs (1 - 12 million equivalent gates, the blocks within the design (250K to 500K equivalent gates or what can be run overnight with Design Compiler) fall under the same rules as multiple-arrays did. The same care in partitioning the I/O (in this case the block interconnect), the grouping of the logic by function and to maintain the best options for the critical paths, and consideration of the external I/O ring requirements are still the rules.
Table 3-1 Components of The Functional specification
Design criteria that are considered as hard (inflexible) specifications should be clearly documented as such. Specifications that might be alterable should also be clearly identified. If a tradeoff or judgment call needs to be made during the remainder of the design project, such information can save time and possibly the project.
Overall design objectives should be clearly identified and documented. These include optimization for speed, power or die size, which translates to minimized inter nal cell utilization and minimized I/O utilization. Since these objectives are in conflict, they should be prioritized.
As a last step, there should be a careful design review of the circuit and system functional specifications, and the partitioning.