Structured Design Methodology
Create the Preliminary Macro Schematic
(When schematics are to be used)
A block diagram with interconnect detail is the next step following the
selection of the array series. The diagram and the ideas for the implementation
of the various modules may be designed from scratch (for a new circuit)
or be a conversion of standard logic (from an existing SSI/MSI/LSI design).
This is usually a hand-sketch or an EWS block schematic, used to plan
what is to be captured in detail later.
These days, this is the" block out the RTL" stage.
An EWS block diagram can serve as the top of a hierarchy drawing set
and be incorporated as an integral part of the drawing set. The block
diagram clarifies boundaries and logic flow between circuit modules and
is useful in determining how many schematic pages will exist. Repetitive
modules can be identified which may affect the method of schematic construction.
- Schematics may be flat (all in one directory and each one stand-alone
- Schematics may be hierarchical, where a block diagram is at the top
and different blocks are defined in subdirectories of one or more pages.
Multiple levels are possible in this approach.
- Schematics may be recursively defined where a series of blocks each
use the same subdirectory and page or pages as the referenced definition.
This type of drawing page organization may be called hierarchical or
nested or something else, depending on the EWS vendor.
The RTL may be classed the same way - and hierarchical designs often have had to be "flattened" before progressing from one EDA tool set to another. The designer needs to be aware of all such limits on hierarchy for every tool being employed in the design from RTL to wafer-fab. Repeated design blocks must be set as "unique" in the design.
Optimize the Design
The existing macros for the particular array or array series chosen for
the implementation should be re-reviewed and the design optimized based
on the available macros. [Control the synthesis process with various control
statements and design constraints.]
Review for Testability
The circuit design should be reviewed for testability and circuit reliability
in the design flow and any changes or additional macros required to make
it testable added now. Controllability and observability issues must both
Deliberate redundancy in a design will mask errors and reduce the potential
fault-grading score. Reconvergent fan-out presents problems to most simulators.
Complex feed-back paths should be reviewed and simplified. Test points
should be considered for any deeply-nested path.
Identify any macros needed but not in the released library.
If the macros available need sizing or performance enhancement to suit
the design, a different macro can sometimes be identified. A custom macro
can be used to provide very specific requirements. Because a custom macro
costs time and money, before a custom macro is requested, re-review the
macro library. There are usually several ways to implement a circuit design,
with varying performance and cell utilization results.
Examine minimization and other simplifications before approaching the
array vendor. (AMCC applications engineering must be consulted before
a custom macro evaluation request can be submitted.)
If a custom macro is the solution, it must be designed and specified
for the target circuit. Custom macros are expensive, are not pre-tested
in silicon, and take some nominal time to develop after they have been
approved for development. Vendors prefer that designs be completed with
the released macro library.
There are other advantages to consulting with the applications engineers.
There are many cases where a problem has been solved with an "in-house"
macro, a macro already under development for a later library release.
When these can be identified by the vendor's applications engineers, a
library patch can be sent to the designer. Note that this procedure also
has an approval cycle.
Libraries are fixed in today's libraries and any changes take time. Macro libraries with pre-defined complex macros are available. These can also be re-useable IP blocks (soft is RTL-level, hard is all layers). All IP needs idetification prior to the start of the design.
Review the Intended Schematic for Size
Will the design fit the intended array? Given the identification of actual
macros to be used while still in the schematic planning stages, review
the internal cell utilization and I/O cell utilization. Compare these
to the target array or arrays.
If the array size is exceeded by a relatively small number of cells,
implement cell-usage-reduction techniques to achieve a fit. A cell utilization
of 100% could mean the array is not routable. If the array size is exceeded
by a large number of any one cell type, the design needs more serious
attention, either to reduce the overall circuit size intended for the
array or to justify a larger array.
It is possible to implement functions in several different ways using
the same macro library. One may be cell-intensive, another may be faster
but hotter, yet another may optimize the design objectives. Try different
This is still a good rule. Try different solutions at the pre-assemble level - examine blocks of the design in detail (5K - 10K equivalent gates). Optimize based on a priority-ordering of the design restrictipons (size, speed, power). Best to do this at the early stages of the design then come head-on with a "show-stopper" during place & Route, when such changes are expensive to make.
Estimate the Internal Pin Count for Routability
Is it routable? The internal pin count estimate can be determined once
the initial macro-based design is blocked. (The actual pin count is available
once the circuit has been captured on an EWS or described to a netlister.)
Both internal cell utilization and internal pin count are used to determine
Other factors influence routability and layout. Performance requirements
may dictate that certain paths be kept short. Other paths may need to
be balanced (have identical metal delays). Desired external pin positions
place other restrictions on placement by limiting pad placement. The types
of macros selected, whether they are high-power, high-speed macros or
high-fan-out drivers, can constrain placement. High-functionality macros
usually have more pin-per-cell density and affect routing.
There are some general rules even when using Design Compiler, or Physical Compiler. 3 nets per pin is a good rule of thumb. Physical compiler will show you "hot spots" - where routing is too dense. If you exceed the 3 nets per pin rule (average), you may have a circuit that cannot be successfully routed. The goal is to distribute the design around on the array to keep heat and density uniform as much as possible.
Review Placement Requirements For the Array
There are design considerations that make placement more restrictive
and complex as listed in Table 2-6. The more placement rules are
involved in a design, the more impact the high internal pin count will
have on the routability of the design.
Table 2-6 Placement Considerations (Sample List)
|Placement Considerations Checklist
| A Ground Must Be Near three-State Enable Drivers
|ECL input Needs to be Isolated from SSO TTL
|400MHz paths (and faster) Must be Isolated
|High-frequency CMOS driving into the array must be isolated from
| SSO Groups must be Distributed
|Three-State and Bidirectional Macros may be Required to be kept
|Busses May Need Grouping
|Added Power and Ground Needs to be Interspersed With the SSO
|Dual Cell I/Os Are Placement-Restricted
|HF I/Os are Package Pin Restricted and Therefore Placement Restricted
|Programmable Overhead Arrays Have I/O Cell Usage vs. Overhead
|Soft MSI Macros have Preferred Placements
|Hard MSI Macros have a Fixed Placement
|Packages May Require Added Grounds
|Clock Distribution for the Design
- Radial for Speed; Fan-out Tree
|Desired Critical Path Placement
Combine internal cell utilization, internal pin count and complexity of
placement to evaluate circuit routability.
There are a few EDA tools around today that can help with routability estimation.