Logic Design for Array-Based Circuits

Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White, WhitePubs Enterprises, Inc.

• Table of Contents
  
• Preface
  
• Overview
  
• Chapter 1 Introduction
• Chapter 2 Structured Design Methodology
• Chapter 3 Sizing the Design
• Chapter 3 Appendix = Case Study in Sizing a Design
• Chapter 4 Design Optimization
• Chapter 5 Timing Analysis for Arrays
  • Introduction
  • Path Propagation Delay Overview
  • Intrinsic Set-Up and Hold Time
  • Intrinsic Recovery Time
  • Set-up, Hold and Recovery Specifications
  • Maximum Operating Frequency; Toggle Frequency
  • Intrinsic Pulse Width
  • Interconnect Delays
  • Types of Extrinsic Loading
  • Annotation
  • Manual Computation - One Method
  • Example Equations for Extrinsic Loading - Internal Nets
  • Lnet - Front Annotation
  • Fan-In
  • Fan-Out - Lfo
  • WireOR - Lwo
  • k-Factors
  • Computing Lfo
  • Computing Lwo
  • Computing Lnet
  • Exercises
  • Example Equations for Extrinsic Loading - Output Nets
  • Q5000 Example (Front-Annotation)
  • Worst-Case Delay Multiplication Factors
  • Exercises
  • Front Annotation
  • Remedial Steps - When a Path is too slow
  • Intermediate Annotation
  • Remedial Steps - Intermediate Annotation
  • Back Annotation
  • Remedial Steps - Back-Annotation
  • Exercises
• Chapter 6 External Set-up and Hold Times
• Chapter 7 Power Considerations
• Case Study: DC Power Computation
• Case Study: AC Power Computation
• Chapter 8 Simulation
• Case Study: Simulation
• Chapter 9 Faults and Fault Detection
• Chapter 10 Design Submission
• ASIC Glossary
  • Glossary A-D
  • Glossary E-K
  • Glossary L-R
  • Glossary S-Z
  • Symbols

Timing Analysis for Arrays

Last Edit July 22, 2001

Back-Annotation

The most accurate method of computing a circuit propagation delay requires that the circuit be completed through layout (routing). Back-Annotation software adds the actual metal delay to the electrical fan-out and wire-OR delays in the path. As for Front- and Intermediate-Annotation, Back-Annotation files provide the net rising and falling edge delays. These files can be used to compute accurate predictive path propagation delays and external set-up and hold times.

Back-Annotation delay files include metal load delays which account for the differences in rise and fall times due to differences in metal load units for the rising and falling edges of metal 1 and metal 2.

This software is undergoing further evolution as RC distributive networks are being examined by several vendors as a possible refinement. There is also research being undertaken to examine the topological effects of the path delays (nearness of a signal on one level to another active signal).

The Back-Annotation software uses a mainframe-based database and is not available on the individual workstations. The program provides files that can be used on the workstations and which include the actual metal delays of each net. The Back-Annotation delay files are used in the simulations in the same manner as the Front-Annotation files.

Back-annotation must be run and accepted as final before the generation of the actual arrays.

Vendors will guarantee that the array will match (will not be slower than) the results of the Back-Annotation.

Back Annotation Load Units Example - specific to the metal layer

Data used to be supplied such that computations had to be made, hence the conversion tables. These computations are now performed by software. Synopsys PrimeTime^TM and DesignTime^TM STA (Static Timing Analysis) imports back-annotation data (PDEF, edif, SDF and RC_parametric file) and performs the sack-annotated timing analysis.

Remedial Steps - Back-Annotation

If Intermediate-Annotation analysis has been performed, the probability of a failure during Back-Annotation analysis is significantly reduced. When a path is having timing problems after routing, the solutions are still those listed before, to reevaluate the problem and to determine an acceptable solution.

Minor problems can often be solved by a post-route edit. More serious problems require a more serious solution, including a return to the design phase. All timing problems must be resolved before committing the design to production.

Exercises

1. For a bipolar array series of interest, how are the intrinsic macro delays specified?
2. For the same series, if worst-case multipliers or adjustment factors are specified, what are they and what operating conditions do they encompass?
3. Repeat 1. and 2. for a BiCMOS array series. Does the technology make a difference to the specification approach? If it does, why does it? If it does not, why not?
4. Are the macros in the bipolar library chosen in step 1. specified as unloaded or loaded?

Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc.
For problems or questions on these pages, contact [email protected]