Logic Design for Array-Based Circuits

by Donnamaie E. White

Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc.



L cell
See logic cell.

Abbreviation for leadless chip carrier. Package type.

Abbreviation for leaded chip carrier. Package type.

Leaded chip carrier

Leadless chip carrier

Light-emitting diode.

Load delays
The amount of time delay caused by loading on the macro due to electrical effects of fan-out loading, wire-OR loading, and the physical metal etch. For output macros, the time delay caused by the system and package pin capacitive loads.

Logic array
An array of predefined base-wafer transistor, diode and resistor components that can be configured into a variety of logical circuits by way of n-levels of metal interconnect. Levels number two or three for semi-custom arrays contain the logic.

Logic cell Internal cell, Function cell
Cells designed for logical functions and not for I/O; can accommodate certain buffers.

Logic functions
See functionality, includes AND, OR, NOT, NAND, NOR, INVERT and combinations of these.

Low-power macro
A macro option designed to use less power than the standard option at the cost of slower propagation delays.

Low-power option
Same as low-power macro; macro options.

Large Scale Integration, from 200 to 1000+ equivalent gates on a chip.

Low power Schottky TTL.


Pre-designed logical function with a name; May be multiple cells.

Macro functions
Logic functions that are performed by the macros in a library.

Macro library
The collected set of macros that are valid for use in a given array or array series.

Macro library element
A macro, either simple (0.5 cell to n cells) or complex.

An integrated set of software tools for logic array design.

Macro options
Variations on the basis macro specification such as low-power, high-power, high-speed, termination or pull-down, pull-up resistors, etc. The propagation time and current specifications of the options will vary from the standard while the function performed does not. Drivers do not usually have options. Different ECL types and power supply configurations are handled by macro versions.

Macro oriented
An array arranged as repeated groups of configurable components in contrast to a "sea of primitive gates" structure.

Macro version
A macro meant for another ECL type (ECL 10K versus ECL 100K) or power supply (+5V REF ECL versus STD REF ECL). The parameters are identical.

A level of interconnect or via (through-holes) defining one layer of a die.

Mask-programmable devices
Example devices are gate arrays and ROMs.

A circuit with one stable state and one quasi-stable state. Also called a one-shot, a delay circuit, a single-cycle circuit, a gating circuit.

Metal-oxide semiconductor Developed for denser, lower performance circuits. Simpler processing and fewer mask layers allow larger circuits to be produced.

Medium Scale Integration. 20-100+ equivalent gates on a chip.

MSI functions
Functions of size/complexity appropriate to MSI devices; Medium scale functions; MUX, decoder, register. See above.

MSI library
A collection of large, multiple cell macros

MSI logic macros
Large, multiple cell macros

Multiplexor, also spelled multiplexer A select one of n device where n input lines are reduced to one output, the nth line active is selected by one or more selection control inputs.


The etch required to connect one output pin to all of its destination pins plus any etch required to connect any other sources wire-ORed to that pin. Also described as "photolitho-graphically determined inter-connect metalization". A wire-net refers to the representation of a net on a circuit schematic. A net segment is a piece of a net from one end to a node.

A listing of all the interconnects within a circuit.

The interconnect point of two or more nets.

Nanosecond, 10-9 sec.


Output cell
A cell that accommodates output-only functions.

Output macro
Macro that performs the translation from internal levels to external levels for a device. Depending on the cell complexity, it may require the use of a buffer or may provide its own.

A data file created and used by AMCCANN.

Overhead circuitry
Overhead circuitry consisting of bias generators and voltage references is pre-defined in the base array.

Overhead current
The current dissipated by the overhead circuitry. It may be a function of the numbers and types of interface macros used.

Another bipolar technology.


The enclosure used to protect the die and interconnect it to the board.

Package power and ground planes
Newer packages provide internal planes to which fixed power and ground pads may be connected. Allow the 1 to 1 ratio of fixed power and ground pads to package power and ground pins to be altered. Allow added power and grounds to connect to internal planes only if placed on pads accessible to the internal planes.

Package signal pin
An external package pin that carries a variable signal level as opposed to one that carries power or ground.

A registered Trademark of Monolithic Memories, Inc. Program-mable Array Logic. An optimized variant of a PLA (more inputs, more outputs, or more functionality by reducing the width of the OR portion of the array). "AND" array user-programmable, "OR" array pre-programmed, groups of product terms are ORed to the y outputs according to the pre-arranged, pre-programmed pattern.

Passive components
Example passive components of a die are resistors, capacitors and conductors.

A printed circuit board has interconnections between points printed in metal on the board. "PC board" could be confused with a personnel computer board.

Pin grid array; A package type suitable for high pin-count requirements, it has pins .100 inch apart on 10x10 through 17x17 matrices brazed perpendicular to the die cavity.

Programmable Logic Array Either AND-OR or NOR-NOR structure.

Ratio of the density (number of gates) to the power (current and therefore heat) possible in a given technology.

Power option
Macro option that provides extra current to drive additional fan-out loads without altering the function or the propagation delay. Used on older families of arrays.

This chip macro parameter is available only to ECL or standard-reference ECL/TTL mixed circuits. For 100% ECL circuits it specifies the standard -5.2V (STD5) or -4.5V (STD4) supply or the +5V reference supply (5VREF). For mixed circuits it specifies either -5.2V or -4.5V. It is used with PRODUCT_GRADE to determine AMCCANN delay file values.

This chip macro parameter is used to identify a circuit as MILitary or COMmercial. Along with POWER_SUPPLY, it is used by AMCCANN to determine the contents of the time delay files (depending on the library).

An array or circuit code name used to identify a design. It appears as a parameter on the chip macro.

Programmable read-only memory; "AND" array, pre-programmed (at the factory), n inputs, 2**n product terms; "OR" array, user-programmable, any of the product terms can be ORed to the y outputs.

Propagation delay
The time it takes a signal to pass through a macro from input to output, specified in typical time in the macro listing in the AMCC Design Manuals.

Picosecond, 10-12 sec.

ECL operating in the TTL voltage range, using +5V and GND. More properly called +5V REF ECL.


True output of a flip/flop or latch.

Complementary output of a flip/flop or latch.


Reset Q output of a latch or flip/flop to FALSE, usually = 0.

RAD-hard Degree of resistance from radiation effects.

Random Access Memory, used to refer to Readable - Writable Memory

Rising-edge active
A flip/flop or device that can change state on the rising edge of the active clock and is static during the falling edge of the active clock.

Read Only Memory

Routing channels
Paths that can be used during layout to complete circuit interconnections. that replaces the static current source of the emitter follower. This allows lower power, higher drives, and reduced skews.

Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc.
For problems or questions on these pages, contact donnamaie@-no-spam-sbcglobal.net