Logic Design for Array-Based Circuits - D. E. White - eBook


Logic Design for Array-Based Circuits by Donnamaie E. White Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc.

Table of Contents Preface Overview Chapter 1 Introduction Chapter 2 Structured Design Methodology Chapter 3 Sizing the Design Chapter 3 Appendix = Case Study in Sizing a Design Chapter 4 Design Optimization Chapter 5 Timing Analysis for Arrays Chapter 6 External Set-up and Hold Times Chapter 7 Power Considerations Case Study: DC Power Computation Case Study: AC Power Computation Chapter 8 Simulation Introduction Simulators - The Tools Non-Native Simulators AMCC's Race Check Timing Verifiers Hardware Emulators Golden Simulators Design Validation Wafer Sort/Packages Part Sort Functional Simulation Fault-Grading Testability Analysis Simulation Rules At-Speed Simulation for Timing Verification AC Tests Parametric Vectors Gate Tree - Any Circuit Hazards Structural Hazard Types Functional Hazards What is Required to Fix Race Problems Exercises Case Study: Simulation Introduction The Schematic Output Enable Clock MUX Enable Design Checks Annotation The Simulations Functional Simulation Parametric Simulation At-Speed Simulation AC Test Exercises Chapter 9 Faults and Fault Detection Chapter 10 Design Submission ASIC Glossary Glossary A-D Glossary E-K Glossary L-R Glossary S-Z Symbols	Simulation Last Edit July 22, 2001 Parametric Simulation Since there is a gate tree, a parametric vector set can be easily constructed using the Minimal Test Sequence. The sequence requires that only one input change per vector, that each input toggle in both directions and that the output (PARAM) toggles with each vector. Figure 8-3 shows a parametric vector file for a 32-bit version of the register. Sampling and format are vendor-specific, and the 100 ns step was used. Note that the reset is executed at the beginning as it was for the functional vectors. This will produce an error message during parametric vector checking. Figure 8-3 Parametric Simulation - 32-Bit Register (partial) Figure 8-3b Parametric Simulation - 32-Bit Register - Full Listing By combining the functional and parametric vectors, 100% fault coverage is obtained for a circuit. Only sampled simulations are submitted. Exercise Create a complete parametric vector set for the schematics shown in the Appendix of Chapter 3.
Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc. For problems or questions on these pages, contact [email protected]