Logic Design for Array-Based Circuits
Structured Design Methodology
Initial Sizing of the Circuit
Before an array or array series has been chosen, estimate the size of the circuit or circuits to be placed on the array. Estimate the number of I/O connections, the types of I/O connections and the I/O cell count. The I/O cell count and the pad count may both be required. Estimate the internal cell count. (See Table 2-4.)
Table 2-4 Sizing Review
For standard functions, equivalent gate counts may exist that can be used in place of internal cell count to estimate the size of the internal array area that will be required. Internal cell counts are more useful than equivalent gate counts where the cells are more complex than one or two gates.
Compare these estimates to the review of the arrays still under consideration and their I/O resources, their internal density and their maximum frequency of operation. Note that, at this stage in the design, the sizing estimates for the circuit may be off by a considerable margin. Historically, device cell utilization at the estimate stage of a design is 20-30% below the final value.
Q2000 Series Approximate Equivalent Gate Size (Historical)
Internal Cell Utilization
The first population checks can be made before the circuit is designed. Internal cell utilization is one of these checks. Internal cell utilization is the number of cells required by a circuit divided by the number of cells available.
Macros that are suitable can be listed and a rough estimate of internal cell utilization computed. This step includes a review of the available macros in the various libraries with emphasis on the requirements of the specific circuit application.
Reviewing the macros available allows a match to be made between functional macros that exist and what is required to implement the design in the least silicon for the highest performance. All other things being equal, the convenience of the macro library can be a decisive factor in the final array selection.
Do the macros available support the circuit modules? Large macros may include adders, carry-look-ahead, comparators, up and down counters, universal registers, large multiplexors and decoders.
Internal cell utilization should be 60-70% at the initial stages of sizing estimates to allow for expansion due to buffers, fan-out load distribution, path balancing or specification changes. The internal cell utilization limit for a completed design is array-specific. (See Table 2-5.) AMCC arrays have an upper limit of 95-100%.
Table 2-5 Internal Cell Utilization Limit
Interface Cell Utilization
The I/O requirements to the outside world are the second size determination. The array for a circuit must provide sufficient I/O capability to handle all signals, all other interface-placed circuit support such as three-state enable drivers, test enable controls and added power and ground pads to support simultaneously switching outputs (SSO) and high-speed inputs.
As with internal cell utilization, only an estimate of final interface cell utilization can be made. The array should not use100% of the I/O or the design will become I/O bound. Pad utilization, for cases where the I/O cells and pads are not one for one, must also be kept under 100%.
A check on array symmetry should be made. The Q20000 Series arrays do not provide the same number of I/O cells in each array quadrant. This may affect placement and added power and ground usage. The Q24008 is not square and has variable power and ground bonding. Check for these and other variations that might affect allowable utilization of the I/O pads and cells.
Selection of the Array Series (Obsolete Methodology)
Integrate the hardware specification, the available arrays and the initial sizing estimates to select the target array series. The final choice is usually based on the performance - cost - availability - support matrix. In cases of equivalence between one or more array series, the final choice may be subjective.
Package availability should be considered in the early decisions since customized packages, especially for large arrays, take months to develop.
The specified performance and requirements for on-chip memory will assist in the reducing the number of options. Only a limited number of arrays support on-chip memory, such as the QM1600T. CMOS and BiCMOS do not yet support designs operating at 300MHz (although individual macros can toggle at these speeds). High-speed bipolar arrays support paths operating over 1.4GHz.