Logic Design for ArrayBased Circuitsby Donnamaie E. WhiteCopyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc. 


Sizing the Design  Selecting the ArrayArray SizingCell StructureEach cell in an array consists of a number of uncommitted transistors, resistors and other discrete components and is designed around the performance criteria for the intended macro library. The cells will vary between array series, regardless of the vendor. Equivalent gatesThe number of equivalent gates has been a design measure dating from the days of discrete designs first converting into SSIlevel ICs. Integrated circuits were classed as SSI, MSI and LSI based on their equivalent gate counts. Circuits were "sized" based on the number of equivalent gates it would take to create them. CMOS arrays carried on with the equivalent gate count and it was reasonable because the internal cell in a CMOS array can be sized as 1, 2 or 3 gates. Bipolar arrays carry equivalent gate counts on their data sheets as a sizing measure but it serves only to show relative sizing between arrays in the same series. Bipolar array cell complexities render equivalent gates a rough measure at best. BiCMOS cells are more complex than CMOS and equivalent gate estimates are not recom mended for them either. To complicate the problem, vendors use many different methods for computing equiva lent gates. The designer would need the algorithms before a rational comparison based on equivalent gates can be made between and two array series, even from the same vendor. Example  Method 1One approach to array sizing is to count the number of transistors in the internal core cells, assume that 2.5 transistors is equivalent to a gate (Digital Equipment's defini tion), and compute the number of equivalent gates per cell. The product of the number of cells times the number of gates per cell provides the equivalent gates per array.
Example  Method 2Another method is to use the D flip/flop. Sizing the D flip/flop as 11 gates, the Q20000 Series D flip/flop uses 2 internal cells.
Example  Method 3The usual AMCC method is to size a 3:1 MUXD flip/flop macro as 11 gates. The Q20000 Series 3:1 MUXD flip/flop uses 3 internal cells.
Example  Method 4The last method discussed here is to size a full adder at 16 gates. For the Q20000 Series, a 1bit full adder takes 3 internal cells.
or:
AMCC ASIC Product Selection Guide with Equivalent Gates Listed (1996) (repeated)
I/O cell contributionsNone of these methods for estimating equivalent gates take the logic capability of the interface cells into account. Some vendors do count them in their published equivalent gate counts and others do not. Example  AMCC cell designAMCC cell design is optimized for MUX, latch and flip/flop implementations. Each cell is designed to support highspeed requirements so that there are no placement re strictions on the highspeed option macros due to cell limitations. No power is used by a cell in its base configuration. For the AMCC BiCMOS arrays, a cell is roughly 3 gates. For the bipolar arrays, a logic cell is a more complex structure and varies with the series. 

Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs
Enterprises, Inc. 