Logic Design for Array-Based Circuits - D. E. White - eBook


Logic Design for Array-Based Circuits by Donnamaie E. White Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc.

Table of Contents Preface Overview Chapter 1 Introduction Chapter 2 Structured Design Methodology Structured Design Methodology Review of the Available Arrays Initial Sizing of the Circuit Create the Preliminary Macro Schematic (when schematics are used) Compute the Path Propagation Delay Compute the Estimated Power Pre-Simultation Steps Simulation Fault Grading Design Submission Through Prototype Design Validation Review Placement Chapter 3 Sizing the Design Chapter 3 Appendix = Case Study in Sizing a Design Chapter 4 Design Optimization Chapter 5 Timing Analysis for Arrays Chapter 6 External Set-up and Hold Times Chapter 7 Power Considerations Case Study: DC Power Computation Case Study: AC Power Computation Chapter 8 Simulation Case Study: Simulationest Chapter 9 Faults and Fault Detectiond Output Chapter 10 Design Submission ASIC Glossary Glossary A-D Glossary E-K Glossary L-R Glossary S-Z Symbols	Structured Design Methodology The Design Submission Through Prototype Complete the Design Validation Review Once the simulations are completed, the entire circuit package should be reviewed for completeness. This is a preliminary design acceptance review. AMCC currently provides a Design Validation form that identifies areas that are characteristically problems in a design submission, a list of items that previous design submissions had in error. After AMCCERC errors, timing check errors and AMCCVRC errors have been resolved, the designer should work through the checks in the Design Validation section of the design manual. These are checks that have not yet been or can never be automated. The questionnaire is incorporated into AMCCSUBMIT, a design submission program that queries the designer for file names and conditions, and produces reports for use in design submission. For array vendors without such a list or automated support, review the submission procedures and the array design rules. Complete the Design Submission Checklist The array vendor will have a submission procedure, a list of the files and documents required for submission before the vendor can accept the design and proceed to layout. Check off the required items as they are assembled into the package. A design cannot be submitted without the completion of the required items. Optional items must be complete if the option is chosen. Last of all, make sure some media index exists in both media and hardcopy form that identifies what is in the submission package. AMCC has created a generic design submission form as a first step in creating a user-interface automation of the design submission - design validation process. It and its accompanying document detail what is required to be submitted in hardcopy and what is to be submitted on media (disk or tape). (The first version of the form is now part of AMCCSUBMIT.) AMCCSUBMIT generates a report that alerts the reviewer to problem areas in the design or the design submission package. Submit the Circuit - Acceptance Design Review When the design submission package is complete, submit it. The vendor will review the package for completeness and correctness. The submission will include all pre-approved design waivers negotiated before submission. If everything has been done according to the vendor's rules, the design will be accepted and move into its proposed schedule. If only minor things are missing or incorrect, the array vendor may make the changes under the designer's approval. If serious errors or omissions exist, the design may be rejected, i.e., returned to the designer with instructions on what is missing or incorrect. Implementation Engineering - the Array Vendor On design acceptance, the Implementation Engineer assigned to the design will rerun all simulations against the in-house library. The object is to identify any macro design changes implemented after the library release date that would affect the design under review. A second objective is to verify that the circuit used on the schematics, netlist and simulations all match since it is easy to violate file consistency.
Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc. For problems or questions on these pages, contact [email protected]