Logic Design for Array-Based Circuits - D. E. White - eBook


Logic Design for Array-Based Circuits by Donnamaie E. White Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc.

Table of Contents Preface Overview Chapter 1 Introduction Chapter 2 Structured Design Methodology Chapter 3 Sizing the Design Chapter 3 Appendix = Case Study in Sizing a Design Chapter 4 Design Optimization Chapter 5 Timing Analysis for Arrays Chapter 6 External Set-up and Hold Times Chapter 7 Power Considerations Case Study: DC Power Computation Case Study: AC Power Computation Chapter 8 Simulation Case Study: Simulation Chapter 9 Faults and Fault Detection Introduction Controllability Observability Masking a Fault Fault Types Fault Equivalencies Single Stuck-At Faults Minimal Test Sets Example Test Set The Problem Combinatorial Circuit Formation Rules for the Existence Function Forming Links Selecting a Chain Advantages of the Test Sequence Simple Gates - Sequences Extension to Three-State and Bidirectional Structures Extension to Sequential Circuits Reference Case Study - 16:1 MUX D Flip/Flop Circuit 100% Fault-Grade Vector Set The Marquand Map 2;1 MUX Example 3:1 MUX Example 16:1 MUX Actual Test Vectors Chapter 10 Design Submission ASIC Glossary Glossary A-D Glossary E-K Glossary L-R Glossary S-Z Symbols	Faults and Fault Detection Last Edit July 22, 2001 The Problem The problem is to construct a complete and minimal test set such that any single fault condition is detected, provided that masking has not covered the effects. Combinatorial Circuit During research into applications of Svoboda's Boolean Analyzer, a method of deriving a Minimal Test Sequence was discovered. It was, at that time, applied to combinatorial circuits and indicated that it could probably be applied to sequential circuits [Svoboda, White, 1974]. Since that time, the method for deriving test sequences for sequential circuits has been developed. The first step in developing a Minimal Test Sequence is the derivation of the circuit equations. These have been found to be implementation-independent. They may be derived on a gate by gate basis from a particular implementation, but the resulting sequence will always be the same as that derived for a minimized implementation of the circuit. Internal nets (intermediate variables) are not required to be in the final equations. If intermediate variables are to be carried through, they are treated as unknowns Primary output variables are treated as unknowns. Primary input variables are the knowns. A primary input is an input that is connected to an external source. A primary output is an output going to an external sink or connection. After all equations for all gates are listed for a circuit, form the Existence Function by solving the equation: ( F = G ) <==> ( y = 1 ) where y is the output. Equations of the form F = G can be rewritten as: ( F G ' + F ' G = 0 ) <==> ( y = 0 ) where F G ' + F ' G = 0 expresses the validity requirements for the complement functions. The Existence Function contains all behavior properties of the circuit. Fault testing problems are solved by adding equations to the system equations or by processing the Existence Function after it is derived.
Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc. For problems or questions on these pages, contact [email protected]