Logic Design for Array-Based Circuits

Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc.

• Table of Contents
  
• Preface
  
• Overview
  
• Chapter 1 Introduction
• Chapter 2 Structured Design Methodology
  
• Chapter 3 Sizing the Design
  • Functional Specification - A Closer Look
  • Review the Available Arrays
  • Architectual Specification or Hardware Specification
  • Array Sizing
  • Cell Capabilities
  • Array Architecture
  • Netlist
  • Example: AMCC Interface Options
  • Example - AMCC Arrays - Power Supply Options
  • Interface Cell Functionality
  • Examples
  • Internal Cell Functionality
  • Multi-Cell Macros
  • Hard and soft macros
  • Refining Interface Requirements
  • Adding Extra Power and Ground Macros
  • Dual-Function I/O Macros
  • Example - Simultaneously Switching Outputs
  • Thermal Diodes
  • The AMCC Speed Monitor
  • Final Interface Cell Utilization
  • Drivers
  • Exercises
• Chapter 3 Appendix = Case Study in Sizing a Design
• Chapter 4 Design Optimization
• Chapter 5 Timing Analysis for Arrays
• Chapter 6 External Set-up and Hold Times
• Chapter 7 Power Considerations
• Case Study: DC Power Computation
• Case Study: AC Power Computation
• Chapter 8 Simulation
• Case Study: Simulationest
• Chapter 9 Faults and Fault Detectiond Output
• Chapter 10 Design Submission
• ASIC Glossary
  • Glossary A-D
  • Glossary E-K
  • Glossary L-R
  • Glossary S-Z
  • Symbols

Sizing the Design - Selecting the Array

Thermal Diodes

As the arrays have become larger and dissipate more power, thermal characterization becomes an increasingly important issue. Some means of evaluating array junc tion temperature must be developed for each array series.

For some of these series, macros have been developed that allow the designer to add one or more thermal diodes to the design. The macros are treated as any other macro and are placed on interface cells.

Newer arrays, such as the Q20000 Series, have thermal diodes built into the base array. The Q20000 Series arrays have a thermal diode structure embedded in the base and brought out to dedicated or fixed pads. These pads must be brought out to package pins. These pads are not accessible to any other macro function.

Example - AMCC thermal diodes (1994)

Thermal diode macros exist for the Q14000 and Q5000 Series libraries and the designer is required to add one thermal diode macro pair per circuit. Using more than one was found to be unnecessary as the thermal gradient across the chips was found to be insignificant. Where there might be doubt, additional thermal diode pairs can be added. Each pair uses two I/O cells. (See Figure 3-8.) One earlier version of the implementation also used one internal cell. No differences were found to exist between these two versions.

Thermal diode macros also exist for the Q20000 Series for those cases where a second thermal diode measurement is felt to be necessary. (Not on the Quicksheets.)

Figure 3-8 Thermal Diode Pair (Not normally for Q20000)

The AMCC AC Speed Monitor

AC testing is a problem for both the designer and the vendor and to reduce the problems associated with it, the Q20000 Series arrays each has a built-in AC speed monitor with two fixed pads assigned to it. These pads must be brought out to package pins.

Threshold Generators - Routable Generators

The designer is not usually concerned with the threshold generators. In cases where they are required, they may only need identification and routing connections rather than actual cell placement.

VBB Reference Voltages

There are some instances where VBB reference voltages are desired, where I/O utilization is high and the designer is using single-rail ECL where differential ECL is required. These reference voltages are supplied with a macro and are placed on an interface cell. They will connect to external package pins.

Speed and Testing Interface Cell Utilization

Maximum speed of operation and testing requirements will have an affect on the final interface cell count. For very high speeds, differential ECL may be required by the array vendor, doubling the cell and pad counts of those signals.

Testing may require that parts of the circuit are degated while other parts are being tested. This will occur when a simultaneously switching group is very large, including the simultaneous enable-disable of three-state or bidirectional macros. Test-enables may be required to partition the circuit for testing, and test enables will use cells and pads.

Population or Cell Type Limits and Utilization

Where population restrictions exist, circumvention of the limits may the include the addition of interface macros. For example, a single-cell bidirectional macro limit would result in two-cell bidirectional macros being used for additional bidirectional signals. The single-cell 25 ohm ECL termination, if dual power supplies are not available would result in two-cell 25-ohm terminations.

Placement Restrictions

High-frequency signals in particular will often require placement in specific cell locations and require that these macros be isolated with added grounds. Added grounds use pads and disable the accompanying cell.

Where placement restrictions require the addition of macros or a change in the macros selected, the effects on cell utilization must be anticipated in the initial estimate.

Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc.
For problems or questions on these pages, contact [email protected]