Logic Design for Array-Based Circuits
Sizing the Design - Selecting the Array
The combination of the macro layout patterns (component interconnect) and the macro interconnect forms the metalization pattern required to implement the circuit on a given array. This pattern is described in a netlist. Each workstation produces a netlist in its own format, carrying along whatever in formation the workstation vendor has decided was necessary. There is no standard workstation or simulator netlist format although efforts are directed toward that goal (see EDIF) and some success has been recently attained.
Parametric information that is included in the netlist is array and array-vendor dependent.
A library such as the Q20000 is shipped to customers with a Macro Parameter File, which supplies the parameters for each macro in the library. These parameters are included in the netlist for each occurrence of each macro used in the design.
Example The AMCC Netlist
To accommodate transfer of designs from any workstation or from any of the sup ported netlisters (Laser 6 and Verilog) to the mainframe-based place and route sys tem, netlist conversion is performed, where the workstation netlist is translated into a standard interface format. AMCC refers to this as AGIF - AMCC generic interface format.
A different conversion program is required for each workstation or simulator that AMCC supports. The standardized netlist is named circuit.sdi . This netlist is used as input to the AMCC MacroMatrix software as listed in Table 3-11.
Table 3-11 AMCC MacroMatrix and Design Support
Interface options - I/O modes
Interface combinations required for the design should be compared to those offered by the arrays under evaluation. The power supply and the interface combination define the I/O mode of the array.
Not all arrays support all possible I/O modes with all possible power-supply combinations.
Once it is seen that the interface mix can be supported on an array series, the type of TTL and ECL outputs that will be required is used to help size the I/O requirements of the array.