Logic Design for Array-Based Circuits

Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc.

• Table of Contents
  
• Preface
  
• Overview
  
• Chapter 1 Introduction
• Chapter 2 Structured Design Methodology
  
• Chapter 3 Sizing the Design
  • Functional Specification - A Closer Look
  • Review the Available Arrays
  • Architectual Specification or Hardware Specification
  • Array Sizing
  • Cell Capabilities
  • Array Architecture
  • Netlist
  • Example: AMCC Interface Options
  • Example - AMCC Arrays - Power Supply Options
  • Interface Cell Functionality
  • Examples
  • Internal Cell Functionality
  • Multi-Cell Macros
  • Hard and soft macros
  • Refining Interface Requirements
  • Adding Extra Power and Ground Macros
  • Dual-Function I/O Macros
  • Example - Simultaneously Switching Outputs
  • Thermal Diodes
  • The AMCC Speed Monitor
  • Final Interface Cell Utilization
  • Drivers
  • Exercises
• Chapter 3 Appendix = Case Study in Sizing a Design
• Chapter 4 Design Optimization
• Chapter 5 Timing Analysis for Arrays
• Chapter 6 External Set-up and Hold Times
• Chapter 7 Power Considerations
• Case Study: DC Power Computation
• Case Study: AC Power Computation
• Chapter 8 Simulation
• Case Study: Simulationest
• Chapter 9 Faults and Fault Detectiond Output
• Chapter 10 Design Submission
• ASIC Glossary
  • Glossary A-D
  • Glossary E-K
  • Glossary L-R
  • Glossary S-Z
  • Symbols

Sizing the Design - Selecting the Array

Netlist

The combination of the macro layout patterns (component interconnect) and the macro interconnect forms the metalization pattern required to implement the circuit on a given array. This pattern is described in a netlist. Each workstation produces a netlist in its own format, carrying along whatever in formation the workstation vendor has decided was necessary. There is no standard workstation or simulator netlist format although efforts are directed toward that goal (see EDIF) and some success has been recently attained.

Parametric information that is included in the netlist is array and array-vendor dependent.

A library such as the Q20000 is shipped to customers with a Macro Parameter File, which supplies the parameters for each macro in the library. These parameters are included in the netlist for each occurrence of each macro used in the design.

Example The AMCC Netlist

To accommodate transfer of designs from any workstation or from any of the sup ported netlisters (Laser 6 and Verilog) to the mainframe-based place and route sys tem, netlist conversion is performed, where the workstation netlist is translated into a standard interface format. AMCC refers to this as AGIF - AMCC generic interface format.

A different conversion program is required for each workstation or simulator that AMCC supports. The standardized netlist is named circuit.sdi . This netlist is used as input to the AMCC MacroMatrix software as listed in Table 3-11.

Table 3-11 AMCC MacroMatrix and Design Support

Interface options - I/O modes

Interface combinations required for the design should be compared to those offered by the arrays under evaluation. The power supply and the interface combination define the I/O mode of the array.

Not all arrays support all possible I/O modes with all possible power-supply combinations.

Interface types

Once it is seen that the interface mix can be supported on an array series, the type of TTL and ECL outputs that will be required is used to help size the I/O requirements of the array.

Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc.
For problems or questions on these pages, contact [email protected]