Logic Design for Array-Based Circuits

Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc.

• Table of Contents
  
• Preface
  
• Overview
  • Introduction
  • Integration Levels
  • Demand and Supply
  • eLearning - the Next Best Thing
    
• Chapter 1 Introduction
  
• Chapter 2 Structured Design Methodology
• Chapter 3 Sizing the Design
• Chapter 3 Appendix = Case Study in Sizing a Design
• Chapter 4 Design Optimization
• Chapter 5 Timing Analysis for Arrays
• Chapter 6 External Set-up and Hold Times
• Chapter 7 Power Considerations
• Case Study: DC Power Computation
• Case Study: AC Power Computation
• Chapter 8 Simulation
• Case Study: Simulation
• Chapter 9 Faults and Fault Detection
• Chapter 10 Design Submission
• ASIC Glossary
  • Glossary A-D
  • Glossary E-K
  • Glossary L-R
  • Glossary S-Z
  • Symbols

Overview

Integration Levels

From the mid-1960s, there are small-scale integration (SSI) gates: NAND, NOR, EXOR, and NOT or INVERT. SSI can be defined to be about 2-10 gates on a single chip. Anything can be built from SSI, but the design time, power, and size make this approach obsolete for designs that must be built quickly and in quantity. Custom design at the transistor and resistor level is reserved for special projects.

From the early 1970s there are larger blocks, medium-scale integration (MSI): registers, decoders, multiplexors, counters, adders, comparators, etc. MSI is loosely defined as approximately 20-100 gates. MSI allows more modular designs, speeding the design process when the blocks could be applied.

In the late 1970s arithmetic logic units (ALUs) with on-board registers, microprogrammable sequencers and interrupt controllers in a bit-slice format became available. Memory chips (ROM, PROM, RAM) in increasing sizes became readily available. Large-scale integration (LSI) culminated in the one-chip microprocessors.

LSI is loosely defined as approximately 200-1000+ gates. Very large scale integration (VLSI) has reached 20,000 gates and higher. LSI and VLSI further increase the modular block size, reducing design time, space, and power considerations and increasing reliability as connections are moved inside the components. Many LSI and VLSI blocks are designed by their manufacturers and referred to as fixed-instruction-set modules.

Bit-Slice Design

For any given design, if the architecture of the fixed LSI and VLSI blocks suit the application then the design time is considerably shortened. When a one-chip microprocessor is not quite suitable, microprogrammable architectures can often provide sufficient customization.

Microprogrammable architectures, such as bit-slice, allow a closer control over the architecture but not total control. The basic building blocks are still designed by the chip manufacturer for generic applications. Bit-slice architectures include interruptable sequencers and 32-bit ALUs.

The customization of the bit-slice modules to an application is done through customer-designed module interconnection, the implemented commands and their sequences. The commands or instruction set is called the micro-program for the design.

ASIC

The 1980s saw the acceptance of ASICs ( application specific integrated circuits), VLSI devices large enough to allow designers to implement architectures that were suited to solving the design problem rather than forcing one architecture to solve everything. It was the natural extension to the bit-slice architectures, where some control of architecture was possible through microprogramming but where the basic building blocks were fixed designs. The application-specific customization of the design solution allows the designer to have the creative power of a gate-level breadboard design while keeping the production advantages of VLSI.

Not far behind the ASIC and ASIC developments, multimedia and design integration saw a need to incorporate analog functions into digital systems. For years the trend had been away from analog design as a chosen career and now there was a shortage of design engineers. First came massive re-training of internal staff as companies struggled to cope. Then came the creation of Electrically Programmable Analog Circuit (EPAC) and related devices.

Now designers are coping with 8-12 inch wafers, 1 million gate chips, a deep submicron technologies with a shrinking design time window. For example, the next-generation Pentium chips are mandated to be first-time silicon success. The first took four tapeouts to achieve success.

Table 2 Integration Sizing Terminology

Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc.
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