Logic Design for Array-Based Circuits

Copyright © 1996, 2001, 2002 Donnamaie E. White

• Table of Contents
  
• Preface
  
• Overview
  
• Chapter 1 Introduction
  
• Chapter 2 Structured Design Methodology
• Chapter 3 Sizing the Design
• Chapter 3 Appendix = Case Study in Sizing a Design
• Chapter 4 Design Optimization
• Chapter 5 Timing Analysis for Arrays
• Chapter 6 External Set-up and Hold Times
• Chapter 7 Power Considerations
  • Introduction
  • Cell Types Define the Power Computation
  • DC Power in a Bipolar Array
  • DCPower in a BiCOMS Array
  • Overhead Current
  • DC Power in a CMOS Array
  • TTL Outputs - CMOS Arrays
  • ECL Static Output Power - All Arrays
  • AC Power
  • Worst-Case Power
  • Adjustment Multiplier for DC Power
  • Checking with the Vendor
  • Power Reduction Techniques
  • The Macros and Their Options
  • Macro Option Examples
  • Design Rules for Macro Options
  • Power-Down and Conditional Geometry - Bipolar
  • Terminated Outputs - Bipolar
  • Terminated Outputs - BiCMOS, CMOS
  • Inverted Outputs for Distotion Management
  • Design Rules for Power Reduction (AMCC)
  • Unused Inputs - Bipolar, BiCMOS
  • MSI and High-Functionality Macros
  • State Dependent Current - Bipolar
  • Computing DC Power Dissipation
  • Steps to Compute Maximum Worst-Case DC Power
  • Reduction for Single-Supply Circuits
  • CMOS and BiCMOS Arrays
  • Design Rules when Power is to be estimated
  • AC Macro Power Dissipation
• Case Study: DC Power Computation
• Case Study: AC Power Computation
• Chapter 8 Simulation
• Case Study: Simulation
• Chapter 9 Faults and Fault Detection
• Chapter 10 Design Submission
• ASIC Glossary
  • Glossary A-D
  • Glossary E-K
  • Glossary L-R
  • Glossary S-Z
  • Symbols

Power Considerations

Last Edit July 22, 2001

Power Reduction Techniques

Regardless of the array technology, items whose use will increase the power dissipated by the array should be carefully chosen. A tradeoff or balance of different design objectives should reflect judicious selections that maintain speed while keeping power dissipation to a minimum and circuit size within the array constraints. Power considerations are no less serious for the large CMOS and BiCMOS arrays.

Table 7-8 summarizes the design choices that contribute to higher power; which choices are possible depends on the array series.

Table 7-8 Power Dissipation Contributors

Table 7-9 summarizes the choices that can be made to reduce power and the design tradeoffs that these may require.

Table 7-9 Low Power Options

Copyright @ 2001, 2002 Donnamaie E. White, White Enterprises
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