Logic Design for Array-Based Circuits

Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc.

• Table of Contents
• Preface
  
• Overview
  
• Chapter 1 Introduction
  
• Chapter 2 Structured Design Methodology
• Chapter 3 Sizing the Design
• Chapter 3 Appendix = Case Study in Sizing a Design
• Chapter 4 Design Optimization
• Chapter 5 Timing Analysis for Arrays
• Chapter 6 External Set-up and Hold Times
• Chapter 7 Power Considerations
• Case Study: DC Power Computation
• Case Study: AC Power Computation
• Chapter 8 Simulation
  • Introduction
  • Simulators - The Tools
  • Non-Native Simulators
  • AMCC's Race Check
  • Timing Verifiers
  • Hardware Emulators
  • Golden Simulators
  • Design Validation
  • Wafer Sort/Packages Part Sort Functional Simulation
  • Fault-Grading
  • Testability Analysis
  • Simulation Rules
  • At-Speed Simulation for Timing Verification
  • AC Tests
  • Parametric Vectors
  • Gate Tree - Any Circuit
  • Hazards
  • Structural Hazard Types
  • Functional Hazards
  • What is Required to Fix Race Problems
  • Exercises
• Case Study: Simulation
  • Introduction
  • The Schematic
    • Output Enable
    • Clock
    • MUX Enable
    • Design Checks
    • Annotation
  • The Simulations
    • Functional Simulation
    • Parametric Simulation
    • At-Speed Simulation
    • AC Test
  • Exercises
• Chapter 9 Faults and Fault Detection
• Chapter 10 Design Submission
• ASIC Glossary
  • Glossary A-D
  • Glossary E-K
  • Glossary L-R
  • Glossary S-Z
  • Symbols

Simulation

Last Edit July 22, 2001

AC Test

An optional simulation is that for AC test measurements. If measurements are to be done, the simulations are required. As with at-speed, both sampled and print on change files are required. Sampling is done at 100 ns intervals. These files show 16 AC tests, propagation path measurements only. A test is one input to one output and one edge (rising or falling). The reset is handled as before at the beginning of the file.

AC test submission is complicated and extensive information is required for each test. AMCC offers AMCCSUBMIT, test submission software, to help with the process. Such support is vendor-specific, as is the vector check software.

Figure 8-6 shows a sampled AC test file (16 tests) and Figure 8-7 shows the same tests, print-on-change. (This is not the Q20000 circuit.)

These files pass the AMCC vector check software.

Figure 8-6 AC Test Sampled Simulation - 32-Bit Register (partial)

Figure 8-6 AC Test Sampled Simulation - 32-Bit Register - Full listing

Figure 8-7a AC Test Print-On Change Simulation - 32-Bit Register (partial)

Figure 8-7b AC Test Print-On Change Simulation - 32-Bit Register - Full listing

Exercise

Create a complete AC test vector set for the schematics shown in the Appendix of Chapter 3.

Exercises

1. For your version of the 32-bit register (assigned earlier), create functional simulation vector files following the rules for the array vendor selected.

2. What other simulations are required?

3. Review the vendor design submission package.

4. What vector checking software tools are available?

5. For the circuit shown, obtain a Q20000 Design Guide and compute the actual maximum frequency of operation for this circuit. (Refer to Chapters 5 and 6.)

6. For your version of the 32-bit register, compute the maximum frequency of operation and the resulting at-speed sample step required for the simulation file.

Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc.
For problems or questions on these pages, contact donnamaie@-no-spam-sbcglobal.net