Logic Design for Array-Based Circuits

Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White, WhitePubs Enterprises, Inc.

• Table of Contents
  
• Preface
  
• Overview
  
• Chapter 1 Introduction
• Chapter 2 Structured Design Methodology
• Chapter 3 Sizing the Design
• Chapter 3 Appendix = Case Study in Sizing a Design
• Chapter 4 Design Optimization
• Chapter 5 Timing Analysis for Arrays
  • Introduction
  • Path Propagation Delay Overview
  • Intrinsic Set-Up and Hold Time
  • Intrinsic Recovery Time
  • Set-up, Hold and Recovery Specifications
  • Maximum Operating Frequency; Toggle Frequency
  • Intrinsic Pulse Width
  • Interconnect Delays
  • Types of Extrinsic Loading
  • Annotation
  • Manual Computation - One Method
  • Example Equations for Extrinsic Loading - Internal Nets
  • Lnet - Front Annotation
  • Fan-In
  • Fan-Out - Lfo
  • WireOR - Lwo
  • k-Factors
  • Computing Lfo
  • Computing Lwo
  • Computing Lnet
  • Exercises
  • Example Equations for Extrinsic Loading - Output Nets
  • Q5000 Example (Front-Annotation)
  • Worst-Case Delay Multiplication Factors
  • Exercises
  • Front Annotation
  • Remedial Steps - When a Path is too slow
  • Intermediate Annotation
  • Remedial Steps - Intermediate Annotation
  • Back Annotation
  • Remedial Steps - Back-Annotation
  • Exercises
• Chapter 6 External Set-up and Hold Times
• Chapter 7 Power Considerations
• Case Study: DC Power Computation
• Case Study: AC Power Computation
• Chapter 8 Simulation
• Case Study: Simulation
• Chapter 9 Faults and Fault Detection
• Chapter 10 Design Submission
• ASIC Glossary
  • Glossary A-D
  • Glossary E-K
  • Glossary L-R
  • Glossary S-Z
  • Symbols

Timing Analysis for Arrays

Last Edit July 22, 2001

Interconnect Delays

Path delays are composed of the intrinsic (t_i, internal to the macro) delays specified for the macros and extrinsic delays (T_ex). Extrinsic delays are composed of the path propagation delays for the macro interconnect (macro to macro routing) and the output macro capacitive load.

For any array, once the macro intrinsic propagation delays for macros in a given path for a given edge direction are listed, the next step in performing timing analysis on a circuit is to evaluate the loading for each macro in the path. Each macro output pin belongs to a separate timing path.

Interconnect delays are the delays incurred by a signal when propagating from a driving macro to the inputs of its load that are caused by the RC time constants of the metal etch interconnect. The delay will be different for rising and falling edges.

For small arrays, the delay was assumed to be dominated by the fan-out loading allowing linear estimates based on that load to be used to approximate the interconnect delays. The interconnect delays in the small arrays were not as large as the intrinsic macro delays themselves, therefore, the simplification could be justified.

As the arrays became larger and faster, the interconnect delay in a heavily loaded net became larger than the intrinsic delay for the macro. It became important to obtain a closer estimate of circuit performance pre-layout. This led to the development of Front-Annotation software, capable of estimating the interconnect delays based on statistical tables of physical fan-out loads versus etch length.

Types of Extrinsic Loading

There are two types of extrinsic loading. The first type exists for those macros that drive internal nets (t_exint).

Loading for an internal net involves:

• the electrical load due to the fan-out for the net;
• the electrical load due to the presence of wire-ORed inputs to the net;
• the physical load due to the first and second layer metal used to interconnect the net.

The net that connects the output macro to the outside world will be subject to a capacitive load. This second type of extrinsic load (t_exout) is due to system capacitive loading and package pin capacitance.

Annotation

There are three approaches that can be used to compute propagation delay due to the interconnect nets:

• Front-Annotation, where a statistical estimate of metal delays based on the physical net size is used;
• Intermediate-Annotation, where a refined statistical estimate based both on the physical size of the net and the relative positions of the macros;
• Back-Annotation, based on the actual lengths of metal 1 and metal 2.

In all three cases, the interconnect delays due to the electrical fan-out load and the electrical loading due to wire-ORs are accurate. The part of the delay due to the metal lengths will vary.

When package pin capacitance is included in the output macro extrinsic load, Front-Annotation uses an estimate since actual placement is unknown. Back-Annotation uses the actual pin capacitance for the assigned package pin.

For critical circuits, since routing is the longest process, Intermediate Annotation can reduce the routing passes or edits required. This tool, however, is not always available.

Drive Factors

Macros are specified with drive capability, drive factors or adjustment factors that apply to extrinsic loading with the same variability that is found in the intrinsic delay specifications. Alternatively, they may have delays directly specified for several loads allowing an extrapolation to be made, often by reading a graph.

Manual Computation - One Method

The path propagation delays can be estimated using:

• the statistical wire delay tables (L_net),
• fan-out loading (L_fo),
• wire-OR loading (L_wo), if any,
• and the appropriate k-factors or drive factors (k) for the macros chosen.

One equation for the typical extrinsic (load) delay for a single internal net is shown below and discussed in detail on the following pages.

One equation for the typical extrinsic (load) delay for a single output net is shown below and discussed in detail on the following pages.

The form and notations used for these equations varies widely with the array vendors.

The typical intrinsic macro delays in the path (tin; specified as Tpd in the macro documentation) and all typical extrinsic loading:

are multiplied by the proper worst-case timing multiplication factor and the results summed. Worst-case macro delays are used directly.

Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc.
For problems or questions on these pages, contact [email protected]