Logic Design for Array-Based Circuits

Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White, WhitePubs Enterprises, Inc.

• Table of Contents
  
• Preface
  
• Overview
  
• Chapter 1 Introduction
• Chapter 2 Structured Design Methodology
• Chapter 3 Sizing the Design
• Chapter 3 Appendix = Case Study in Sizing a Design
• Chapter 4 Design Optimization
• Chapter 5 Timing Analysis for Arrays
  • Introduction
  • Path Propagation Delay Overview
  • Intrinsic Set-Up and Hold Time
  • Intrinsic Recovery Time
  • Set-up, Hold and Recovery Specifications
  • Maximum Operating Frequency; Toggle Frequency
  • Intrinsic Pulse Width
  • Interconnect Delays
  • Types of Extrinsic Loading
  • Annotation
  • Manual Computation - One Method
  • Example Equations for Extrinsic Loading - Internal Nets
  • Lnet - Front Annotation
  • Fan-In
  • Fan-Out - Lfo
  • WireOR - Lwo
  • k-Factors
  • Computing Lfo
  • Computing Lwo
  • Computing Lnet
  • Exercises
  • Example Equations for Extrinsic Loading - Output Nets
  • Q5000 Example (Front-Annotation)
  • Worst-Case Delay Multiplication Factors
  • Exercises
  • Front Annotation
  • Remedial Steps - When a Path is too slow
  • Intermediate Annotation
  • Remedial Steps - Intermediate Annotation
  • Back Annotation
  • Remedial Steps - Back-Annotation
  • Exercises
• Chapter 6 External Set-up and Hold Times
• Chapter 7 Power Considerations
• Case Study: DC Power Computation
• Case Study: AC Power Computation
• Chapter 8 Simulation
• Case Study: Simulation
• Chapter 9 Faults and Fault Detection
• Chapter 10 Design Submission
• ASIC Glossary
  • Glossary A-D
  • Glossary E-K
  • Glossary L-R
  • Glossary S-Z
  • Symbols

Timing Analysis for Arrays

Last Edit July 22, 2001

Intrinsic Set-Up and Hold Time

The intrinsic set-up and hold times represent the required behavior of the signals coming into the macro, observed at its input and output nodes. External set-up and hold times are concerned with the signals at the external pins of the array.

Set-up time (Tsu) is the length of time that a data signal must be stable before the 50% point of the next active clock edge. A negative set-up time indicates that the data does not have to become stable until after the active clock edge.

Hold time (Th) is the length of time that a data signal must be held stable after the active clock edge. A negative hold time indicates that the data can be removed before the active clock edge.

Whether a set-up or hold time is negative is a function of the disparity in the delays in the clock and data paths between the input and the actual functional use of the signal. For example, a complex macro may have a multiplexor in the data path and nothing in the clock path for an internal flip/flop.

Today's libraries tend toward rising-edge active clocks, zero hold times, and positive set-up times.

Start and End Points for Set-Up and Hold-Time Computations

Set-up time is considered to be the minimum time required for a signal to travel from the circuit data pin input to the data port of the flip/flop or register. It can also be the minimum time for a signal to leave the Clk->q port of one register and arrive at the data port of a sequential register (register-tegister delay time).

When the start point is the external data pin (and the clock from the external clock pin), this is considered external set-up and hold time. This is discussed in Chapter 6.

Intrinsic Recovery Time

Recovery time (Trec) is specified for any latch or flip/flop macro that has a set or reset pin, or any complex macro that contains the equivalent function. It is the length of time that a reset or set signal has to have been inactive before an active clock edge. Clocking within the recovery time will result in unpredictable behavior.

Set-up, Hold and Recovery Specifications

Set-up time (Tsu), hold time (Th), and recovery time (Trec) may be specified as typical, in which case adjustment factors or worst-case multipliers must be used to adjust them to the specific operating conditions of the circuit. They may be specified as worst-case for common operating conditions, i.e., Commercial and Military. In cases where differences between Commercial and Military are minimal, only one value may be specified.

Maximum Operating Frequency; Toggle Frequency

The maximum operating frequency (fmax) is specified as the maximum switching rate for the macros and is technology dependent. Macros must not be driven beyond their specified operating limits.

The actual frequency at which a circuit may operate must be computed from the worst-case critical path propagation delay timing analysis and set-up and hold analysis. The limit for a macro is its minimum pulse width: the minimum pulse that can be successfully propagated through the macro. The pulse reaching a macro input pin is a function of the frequency of the signal on that pin and the pulse stretch-shrink distortion of the signal.

Intrinsic Pulse Width

Minimum pulse width (PW) is the inverse of the specification of the toggle frequency for the macro. It defines how close any two edges of a pulse passing through the macro may be. Latches and flip/flops and the complex macros that include these devices will normally be specified with a minimum pulse width and a maximum frequency of operation, possibly differentiated for military and commercial operation, or both. (The reciprocal of the pulse width multiplied by two is the frequency.)

For most macros, the generic maximum frequency of operation for a given class of macros defines the limits. For special cases, such as latches, flip/flops, and complex macros, the macro may have its own specific limits. Complex libraries with a range of performance within the macro set may specify a maximum frequency and pulse width for each macro.

Examples

As an example of specification approaches, the Q20000 [as of 1992-4] specification approach is detailed below.

For Q20000 Bipolar Array Series:

• The pulse width specifications in the AMCC Q20000 design manual are worst-case times, computed from the maximum frequency of operation (assuming a 50% duty cycle).
• PW is specified for Military and Commercial conditions (originally specified for Hot and Cold conditions).
• Tpd delays are specified as unloaded delays.
• Set-up and Hold times are specified as worst-case.
• Although Tsu, Th, and pulse width are specified as single values for the given conditions, the Tpd delays are specified as a min/max range.

For today's Arrays

• Pulse width, set-up and hold times, are computed by today's synthesis programs using data specified in the chosen design library.
• Libraries are specified for specific operating conditions - NO ADJUSTMENTS
• If variations on the library operating conditions is desired, get the vendor to supply a new library. [We will repeat this warning.]
• Each library has 1-2 interconnect models (worst-case being one of them)
• MIN-MAX anaysis of hold time is commonly computed pre-layout to identify serious hold-time issues.
• Individual macros contain set-up and hold time information for the macro.
• Pulse-swallowing is used to refer to the condition where the signal is too fast for the macro to "see" - i.e., the frequency exceeds the minimum pulse wodth fo the macro

Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc.
For problems or questions on these pages, contact donnamaie@-no-spam-sbcglobal.net