Logic Design for Array-Based Circuits

by Donnamaie E. White

Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc.




Each of the last six decades has seen a new technology come forward as the leading edge for that era. Table 1 provides a summary of this evolution by decade and integration level.

Table 1 - Integrated Circuit Evolution

Approx. Date Size Description
1950s gate level A few transistors and other components combined to form an AND, OR or NOR gates
mid 1960s SSI 4 or more gates; NAND, NOR, OR, AND, EXOR, NOT or INVERT
early 1970s MSI up to 200 gates; registers, decoders, multiplexors, etc.
late 1970s LSI several hundred gates; ALUs with scratch-pad registers, interrupt controllers, microprogram sequencers, ROMs, PROMs
1980s VLSI 700 gates and up; CPUs, complex functions
1980s ASIC up to 30,000 gates; multiple functions
early 1990s ASIC up to 100,000 gates and increasing with speeds at 1.4GHz and higher
1980-1990s EPAC The development of analog circuit arrays


Deep SubMicron (< 0.18µ) designs; 1 Million gate arrays; System on a Chip
Intellectual Property - soft and hard IP building blocks
2000 and up Design Reuse (IP);
Deep SubMicron (0.13µ) designs; 4-10 Million gate arrays; more gates, faster designs; improved test methodology; faster synthesis
the 1 GHz and faster CPUs

Each technology change has led to a period where those designers who are state-of-the-art orientated, those who readily delve into new developments, accept and begin to use the newest devices in designs.

For successful technologies, this is followed by the intense application and development phase where the high demand for engineers who can design with the devices typically exceeds the supply of those engineers. The is the driving force behind the evolution of IP (Intellectual Property) blocks, predesigned mega-function blocks that can be re-used in more than one chip.

These mega-functions become part of the design library.They may be hard-IP, where all levels of the base die are involved, or soft-IP, where only the metallization layers (currently about 6-8 layers of the die) are involved.

Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc.
For problems or questions on these pages, contact donnamaie@-no-spam-sbcglobal.net