Logic Design for Array-Based Circuits

by Donnamaie E. White

Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White, WhitePubs Enterprises, Inc.


Timing Analysis for Arrays

Last Edit July 22, 2001


There are two types of timing analysis required for array verification

  • path propagation delay and
  • set-up and hold time analysis.

Path propagation delay is covered in this chapter. External set-up and hold time is covered in Chapter 6.

One circuit design objective is speed and, before schematic capture, a preliminary timing analysis of the critical paths of a circuit is performed. It may be done by simulation or even by hand, if necessary, to assure that the circuit as implemented on the chosen array will be successful. This initial analysis may dictate the design optimization techniques required to ensure that the circuit will meet the specified performance requirements.

To reduce manual effort, as soon as a macro library is available for evaluation, the critical performance paths of the circuit should be captured and a detailed, annotated simulation performed. (Manual computations may still be required for external set-up and hold time analysis.)

A detailed timing analysis of the complete circuit and its critical paths is required before a circuit can be submitted for place and route.

Timing analysis of a circuit includes:

  • worst-case path propagation delays for both rising and falling-edge inputs for all critical or suspected critical paths;
  • external and internal set-up, hold and recovery times;
  • pulse skew and tracking due to placement (process variation);
  • pulse distortion due to wire-OR, fan-out and metal loading (pulse stretch, pulse shrink) for all input and internal macros;
  • pulse distortion due to output macro loading (package pin capacitance and system capacitive loading

The macros selected, the options of those macros, the loading on the macros, and the final layout of the circuit are all factors in the propagation delay of any path. The loading may be the interconnect capacitance or the external load capacitance due to system loading and package pin capacitance.

Path Propagation Delay Overview

Computation of the propagation delay for a circuit path includes an evaluation of the following:

  • input, logic and output macro intrinsic propagation delays
  • extrinsic loading devices
  • an adjustment for environmental effects and processing variations (worst-case timing multiplier) for those arrays which specify typical intrinsic delays

Intrinsic Delays

Array vendors use a variety of design manual documentation formats to specify intrinsic delays. Intrinsic delay (Tpd) is the time required for a signal to propagate from a macro input pin to a macro output pin. The delay may be different for each input to output path through the macro. The delay may be specified as dependent on the input and output edges such as rising to rising (++) or rising to falling edges (+-, inversion). The delay may be a function of other input states or simultaneous input switching. This information is usually detained in the documentation for the macro library.

The four input-output edge combinations may be identified as:

Tpd ++ rising edge input, rising edge output
Tpd +- rising edge input, falling edge output
Tpd -- falling edge input, falling edge output
Tpd -+ falling edge input, rising edge output

Intrinsic delay may be specified as typical, with adjustment factors or worst-case delay multipliers supplied to allow maximum and minimum delay computations for specific operating conditions. The delays may be specified as worst-case maximum for one set of operating conditions with adjustment factors to convert to other conditions. Another option is to specify the delays with a worst-case min-max range for one or more sets of operating conditions. (See Table 5-1.)

Table 5-1 Tpd Specifications And Adjustment Factors (Historical)

Tpd Specified:
For Specific Operating Conditions Use:
Typical Adjustment Factors
Worst-Case Factors for other Conditions
MIN/MAX Range (Specific to Conditions)

Macro intrinsic delay values may assume no loading, one load, or several loads on the macro output pin. When annotation software is available, macros are specified as unloaded.

For some macros, delays are dependent on how many other pins on the macro are also switching. The actual macro path delay may be a function of:

  1. state of the input data (low data may have different set-up and hold times than high data;
  2. low to high (rising edge) propagation may be different from high to low (falling edge) propagation);
  3. multiple inputs changing state (when several OR/NOR inputs change simultaneously, the delay increases).

Three-state macros have specifications for high-Z, representing switching delays for TPHZ, TPZH, TPZL and TPLZ.

The propagation delay supplied in a design manual is for the delay from input to output measured at the 50% level. For TTL I/O macros, the measurement is at the 1.5V level. Rise and fall time is measured between 10% and 90%. The data sheet for the array series should indicate measurement points and levels.

If this information is important to the design, check to see if it is available, under what conditions the measurements were taken and under what load. Adjust according to the intended operating environment and load conditions.


Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc.
For problems or questions on these pages, contact donnamaie@-no-spam-sbcglobal.net