Logic Design for Array-Based Circuits
Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White, WhitePubs Enterprises, Inc.
External Set-Up and Hold Times
Last Edit July 22, 2001
Case 2: When The Timing Specifications Are Worst-Case
For the case where the vendor has specified timing delays as worst-case, the following procedures can be applied. Note that if the macro intrinsic delays are specified as worst-case maximum, some means of computing the worst-case minimum for the same operating conditions must exist.
Set-Up Time - Generic Equation
When computing the set-up time, it is desirable to assume that the data propagation path delay is the worst-case maximum and that the clock path propagation delay is a worst-case minimum for the operating conditions. The generic equation is:
Hold Time - Generic Equation
When computing the hold time, it is desirable to assume that the data propagation path delay is the worst-case minimum and that the clock path propagation delay is a worst-case maximum for the operating conditions.
The generic equation is:
Example - The AMCC BiCMOS Q14000 Series
The Q14000 Series has a complex arrangement of worst-case multipliers, separating interface and internal and differentiating between the channelled and channel-less arrays. For the Q14000 BiCMOS arrays, the data and clock paths are broken down into the interface macro and its net (tDinput or tCinput), and the internal macros and the nets they drive (tD or tC). Both set-up and hold times are specified as nominal for this array.
For the Q14000 Series and its dual multipliers, the external set-up and hold time equations become:
Table 6-1 General Equations When Worst-Case Multipliers Are Used
Table 6-2 provides the external set-up and hold equations for the Q14000 BiCMOS Series Arrays for four defined operating conditions, MIL, COM5, COM4 and MIN, using the specified worst-case delay multipliers specified for the array series for those conditions.
Note that, since these arrays specify nominal macro intrinsic set-up and hold times, the worst-case time delay multipliers are applied to the set-up and hold times as well as to the Tpd delays. This may not always be the case. (Refer to the AMCC Q5000 and Q14000 Design Manuals.)
Table 6-2 Set-Up And Hold Equations BiCMOS Q14000 Series Arrays Q28000B, Q14000B, Q6000B And Q800B Arrays
These equations are for the channelless arrays, those designed with a sea-of-gates or sea-of-cells architecture. (Refer to the AMCC Q14000 Design Manual for the equations for the other arrays in the series that are channelled.)
Which Equations Should be Used?
For external set-up time, use the following as a guideline:
For external hold time, use the following as a guideline: