Logic Design for ArrayBased Circuitsby Donnamaie E. WhiteCopyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White, WhitePubs Enterprises, Inc. 


External SetUp and Hold TimesLast Edit July 22, 2001 Case 2: When The Timing Specifications Are WorstCaseFor the case where the vendor has specified timing delays as worstcase, the following procedures can be applied. Note that if the macro intrinsic delays are specified as worstcase maximum, some means of computing the worstcase minimum for the same operating conditions must exist. SetUp Time  Generic EquationWhen computing the setup time, it is desirable to assume that the data propagation path delay is the worstcase maximum and that the clock path propagation delay is a worstcase minimum for the operating conditions. The generic equation is:
Hold Time  Generic EquationWhen computing the hold time, it is desirable to assume that the data propagation path delay is the worstcase minimum and that the clock path propagation delay is a worstcase maximum for the operating conditions. The generic equation is:
Example  The AMCC BiCMOS Q14000 SeriesThe Q14000 Series has a complex arrangement of worstcase multipliers, separating interface and internal and differentiating between the channelled and channelless arrays. For the Q14000 BiCMOS arrays, the data and clock paths are broken down into the interface macro and its net (t_{Dinput} or t_{Cinput}), and the internal macros and the nets they drive (t_{D} or t_{C}). Both setup and hold times are specified as nominal for this array. For the Q14000 Series and its dual multipliers, the external setup and hold time equations become: Table 61 General Equations When WorstCase Multipliers Are Used
Table 62 provides the external setup and hold equations for the Q14000 BiCMOS Series Arrays for four defined operating conditions, MIL, COM5, COM4 and MIN, using the specified worstcase delay multipliers specified for the array series for those conditions. Note that, since these arrays specify nominal macro intrinsic setup and hold times, the worstcase time delay multipliers are applied to the setup and hold times as well as to the Tpd delays. This may not always be the case. (Refer to the AMCC Q5000 and Q14000 Design Manuals.) Table 62 SetUp And Hold Equations BiCMOS Q14000 Series Arrays Q28000B, Q14000B, Q6000B And Q800B Arrays
These equations are for the channelless arrays, those designed with a seaofgates or seaofcells architecture. (Refer to the AMCC Q14000 Design Manual for the equations for the other arrays in the series that are channelled.) Which Equations Should be Used? For external setup time, use the following as a guideline:
For external hold time, use the following as a guideline:
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Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs
Enterprises, Inc. 