Logic Design for Array-Based Circuits

Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc.

• Table of Contents
  
• Preface
  
• Overview
  
• Chapter 1 Introduction
  
• Chapter 2 Structured Design Methodology
• Chapter 3 Sizing the Design
• Chapter 3 Appendix = Case Study in Sizing a Design
• Chapter 4 Design Optimization
• Chapter 5 Timing Analysis for Arrays
• Chapter 6 External Set-up and Hold Times
• Chapter 7 Power Considerations
• Case Study: DC Power Computation
• Case Study: AC Power Computation
• Chapter 8 Simulation
• Case Study: Simulation
• Chapter 9 Faults and Fault Detection
  • Introduction
  • Controllability
  • Observability
  • Masking a Fault
  • Fault Types
  • Fault Equivalencies
  • Single Stuck-At Faults
  • Minimal Test Sets
  • Example Test Set
  • The Problem
  • Combinatorial Circuit
  • Formation Rules for the Existence Function
  • Forming Links
  • Selecting a Chain
  • Advantages of the Test Sequence
  • Simple Gates - Sequences
  • Extension to Three-State and Bidirectional Structures
  • Extension to Sequential Circuits
  • Reference
• Case Study - 16:1 MUX D Flip/Flop Circuit
  • 100% Fault-Grade Vector Set
  • The Marquand Map
  • 2;1 MUX Example
  • 3:1 MUX Example
  • 16:1 MUX Actual Test Vectors
• Chapter 10 Design Submission
• ASIC Glossary
  • Glossary A-D
  • Glossary E-K
  • Glossary L-R
  • Glossary S-Z
  • Symbols

Faults and Fault Detection

Last Edit July 22, 2001

Introduction

In any circuit composed of logic gates there is the possibility of the occurrence of a fault. A fault is defined to have occurred when any circuit output variable assumes a value of 1, 0 or X that differs from the value expected. When this occurs, the circuit violates the original circuit equations.

Fault detection requires that a vector test set provide a test to detect when any fault has occurred in a circuit path. Fault location requires that sufficient tests be included such that the specific node in failure can be located. In general, fault location requires a larger vector set.

Controllability

A circuit is judged on the ease and ability of the input variables to set internal and output variables to specific values. This is defined as circuit controllability. The ideal case is when internal variables can be set with one input vector (input variable configuration). The worst cases require that multiple vectors be gated through the circuit until a target internal node is set or forced to a desired value.

Observability

A circuit is judged on the ease and ability to propagate the values on input and internal variables to a primary and therefore observable output. This is defined as circuit observability. The best case is when an internal variable propagates directly to an observable output within the vector time step. The worst cases require that multiple vectors be gated through the circuit until a target internal node has propagated to an observable output. In extreme cases, a fault may be undetectable.

Masking a Fault

The presence of an internal or input fault may not be observable at any circuit output. In this case the fault is considered to be masked. A single fault may be masked as the result of the causes shown in Table 9-1.

Masked faults are undetectable by definition since the observed circuit behavior is correct.

The occurrence of a second fault may uncover a previously undetectable fault. To be complete, a vector test set must include tests for this case.

Table 9-1 Single Fault Masking

• reconvergent fan-out where unequal parity changes have occurred
• circuit redundancy, deliberate or otherwise
• previous occurrence of an undetectable fault

Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc.
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