Logic Design for Array-Based Circuits

by Donnamaie E. White

Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc.




This glossary contains industry-standard as well as AMCC - specific definitions. For AMCC software and files, refer to the AMCCERC User's Guide for further information on the items, if you can find one..

3-level gating
Circuit design technique used internally in the AMCC Bipolar Logic Arrays for improved logic density.


AC Speed Monitor
AMCC incorporated a 9-stage ring oscillator followed by a 2-state divide-by-4 counter as the basis of the monitor in the base array for the Q20000 Series arrays. Its use relieves the designer of developing AC test vectors to check part performance. It requires two pads.

AC test
Testing performed with a tester and the packaged part and designed to sample the timing characteristics of the actual die to verify the timing of the actual circuit as produced. Only a few tests are needed since all paths on any single path will be similarly affected by the processing and environment and all timing delays are constrained to be within the temperature-voltage-process variation range.

Active components
Active components of a die are transistors and diodes.

Added ground
Interface cells may be designated as providing ground pads for either IEVCC or ITGND (0V). IEVCC is ground for standard reference ECL. Placement is user-controlled.

Added power
Interface cells may be designated as providing power pads for either IEVCC or ITPWR (+5V). IEVCC is power for +5V REF ECL. Placement is user-controlled.

Adjustment factor
A multiplier specified to allow conversion of a data value specified under one set of conditions to a value suitable for a second set of conditions. They may be used for typical to worst-case maximum or minimum conversion. Factors may be used to adjust for power-supply, temperature or process variation. See worst-case multiplier.

AMCC generic interface format; Used as the means of communicating between a workstation and the AMCC proprietary software tools.

The arithmetic-logic unit, where data is processed according to the instruction under execution.

AMCC annotation software. See also Front-Annotation and Back-Annotation.

AMCC place and route system.

AMCC engineering rules check software. See ERC.

Report produced by AMCCERC.

List of all pads on the array with descriptions of levels and types produced by AMCCERC.

The packaging database shipped with MacroMatrix to allow placement to be completed in the filed. It allows a package to be selected and more refined estimates in the Front-Annotation delays files.

The documentation of the package, package pin capacitance and system load capacitance produced by AMCCANN using the user-interface, interactive input and the output.dly cumulative edits file.

AMCC simulation format preparation software program. Operates (currently) on LIST file input. Unique for each workstation simulator, versions exist for Dazix, Verilog, Mentor, Lasar, and Valid.

AMCC submission automation software. Prompts user for data and provides some screening of the specifications vrs. the annotation results. Produces reports for use in design submission.



Reports produced by AMCCSUBMIT.

AMCC vectors rules checking software. Provides some screening of vectors for functional, AC test, and parametric simulations.

Vector rules check reports produced by AMCCVRC.

A cross-reference listing produced by running the AGIF netlister.

Asynchronous reset. See R.

Asynchronous set. See S.

A circuit with two quasi-stable states; an oscillator.

At-speed simulation
A simulation designed to examine the timing integrity of a circuit design by functioning the circuit at its specified maximum operating frequency.

Autoplace or auto place.
Macro placement on internal array cells is performed automatically by software.

Autoroute or auto route
. Interconnection of the macros is performed automatically by software.


B cell
Old Usage: Buffer cell; can be used for some logic macros as well. Located around the periphery of the internal cell block in AMCC Q700 Series arrays and in the Q1500A Array. Capable of a higher row current limit (three times greater) than the logic cells. New Usage: Basic cell, the internal cells in the BiCMOS arrays

The method of simulation of a circuit after layout, where the loading on a particular net is the sum of the actual fan-out load (electrical load), the actual wire-OR load (electrical load), and the actual metal used to interconnect the pins. The load is a function of the array (die-size) and is accurate within measurement device parameters.

Frequency range of performance for a device (as in the bandwidth of an amplifier).

cell In the BiCMOS Gate arrays, a basic cell is an internal cell, similar in application to the bipolar array L cell.

A back-annotation delay file where xxx[x] identifies the product_grade and power_supply, and ews defines the simulator or workstation for which the file has been formatted.

Capable of moving in either of two directions at any given time.

Bidirectional I/O cells
Capable of processing input or output signals. See I/O cells.

The base two number system where each digit is a power of two, the allowed digits are 1 and 0. In circuit representations of a binary equation the digits 0 and 1 are also called LOW and HIGH or TRUE and FALSE, the equivalent values of which depend on the polarity of the system.

One silicon technology used in ICs; radiation-resistant, faster than CMOS at the expense of higher power dissipation.

One Boolean digit: 0 or 1. X or # are the symbols used for "Don't care" and U is used for undefined or unknown.

Originally meant enough bits to represent a character (code dependent in size); by default a byte is now usually taken as 8 bits. In 16-bit architectures, it is half a word.

A group of single wires; a bus.


Computer-Aided Design.

Computer-Aided Engineering.

Computer-Aided Instruction.

Computer-Aided Manufacturing.

The smallest uniform repeatable unit on a logic array; there may be more than one type on a given array. A cell may or may not be the smallest addressable unit one the array. A cell denotes a group of active and passive elements on an array.

Cell utilization
A measure (percentage) of the number of internal cells actually used in a design (accessible by a designer). The suggested limit is usually specified on the array series data sheet. Internal cell utilization is a more descriptive phrase.

Slang for integrated circuit; it is used for a packaged die.

Chip macro
A pseudo-macro that is used with an AMCC library as a method of communicating circuit and array-specific information to the software. E.g., array, cell count limits, cell types, overhead current, power-supply, product-grade, worst-case multipliers for current and time, if needed, power limit, cell usage limits, cell utilization, pad counts, and other data.

A logical function or functions constructed from electrical devices.

A data file produced by AMCCAD that contains the actual package pin capacitance by signal name, produced after placement.

The AMCC universal netlist produced by translating the workstation or simulator-unique netlist into the AMCC generic interface format (AGIF).

Circuit building block
The basic unit available to simplify circuit design. SSI, MSI, LSI and VLSI represent the evolution of hardware building blocks.

Circuit density
A measure of the number of equivalent 2-input NOR gates a design would require, usually rounded to the nearest 100 or 1000(K) as in "800 gates" or "28K gates".

Clock, CLK , Clock signal
In many AMCC macros the rising edge is taken as the active edge. Either edge may be the clocking or active edge in a circuit or a macro; complex systems use both edges to operate latches and registers.

Current mode logic is a variant of ECL. The AMCC Q20000 Series has CML macros. These are high frequency (600MHz up to >1.2GHz) macros. Terminated with 50 ohms to GROUND, they maintain a typical 500 mV swing.

complementary metal-oxide semiconductor. (In contrast to NMOS - N-channel metal-oxide semiconductor, PMOS - P-channel metal-oxide semiconductor.) Constructed using comple-mentary (N- and P-) MOS field-effect transistors. CMOS has lower power consumption per gate and the highest gate densities per die. See MOS.

Common clock
Reference to using the same clock signal on all devices on a board or all functions within a semi-custom array. A single common clock is the preferred and the simplest method of design. It is also easier to test.

Configurable cells
Able to be altered to fit a particular application.

Conventional ECL
Standard REF ECL, ECL 10K or ECL 100K, voltage supplies are -5.2V (ECL 10K) or -4.5V (ECL 100K).

Internal-net only delay files produced by AMCCAD for use by AMCCANN where xxx[x] identifies the product_grade and power_supply, and ews defines the simulator or workstation for which the files are formatted. Combined with output.dly and circuit.pkg, these files allow the creation of the BCKxxx[x].ews files.

Critical path
The longest path (largest propagation and loading delay) through a circuit.

Custom macro
One that is designed specifically to meet the customer's requirement and is not currently in the released macro library


Delay offset
Lag, time before start.

Design element
Basic part of a design.

Demultiplexor Demux;
A decoder; a device that allows one or more input lines to select between n output lines where the number of inputs is less than the number of outputs.

design automation DA
The tools used to automate the design and design verification from circuit creation to mask specification.

Design rule verification
Software that performs the function of circuit-level design rule verification, or verification that electrical restrictions have not been violated. Wafer fabrication design rules (DRC) are a set of electrical and minimum physical parameters that can be guaranteed for the process.

Another identification for a booked circuit. It appears as a parameter on the chip macro.

The silicon chip itself; plural is dice. A die is an non-packaged chip.

Differential ECL inputs
Pairing of true and complement signals to allow dual-rail communication for increased noise immunity. Required for remote signals, off-board communication with +5V REF ECL and when operating at 80 MHz and higher.

An internal macro that provides extra drive capability, extra current and can handle extra loads. A driver macro typically has lower valued k-factors and therefore can drive more loads at less time delay penalty than a standard macro. The k-factors may be balanced.

Dual-in-line DIP
Type of package with leads perpendicular to the cavity and spaced .100 inch from each other on the same side and .300, .400 or .600 apart from the leads on the opposite side. Many low external pin count (< 64) circuits are packaged in DIPs. Power limitations are about 1 Watt.


Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc.
For problems or questions on these pages, contact donnamaie@-no-spam-sbcglobal.net