Logic Design for Array-Based Circuits
Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White, WhitePubs Enterprises, Inc.
Last Edit September 2, 2001
At-Speed Simulation Submission (Required)
The submitted at-speed simulation is rerun after layout to verify the actual timing performance for the array. The Back-Annotation delay file, which provides the actual metal delays for the layout, is used in place of the Front-Annotation delay file. The circuit.pkg file provides package pin capacitance based on final placement to replace the estimates for package pin capacitance in the output.dly file.
At-speed simulation results provide an evaluation of the timing performance and help identify timing violations and potential timing problems. The customer must supply all at-speed simulation vectors.
AMCC requires that at-speed simulations be performed at the specified maximum operating frequency, and be performed using the minimum library and then again using the maximum worst-case library. Refer to Volume I, Section 3 for the specific series to determine which library is maximum and which minimum for the array.
The at-speed simulation, if required, should be performed following the procedures described in the design manual.
At-Speed Simulation Documentation
The documentation required for at-speed simulation submission is prompted for by the AMCCSUBMIT program interface. Before running AMCCSUBMIT, simulation files for the paths, both in sampled and in print-on-change format should exist. All AMCCSUBMIT errors should be resolved prior to submission.
Documentation included on disk or tape for the sampled at-speed simulation file includes:
Documentation included on disk or tape for the print on change at-speed simulation file includes: