Logic Design for Array-Based Circuits

Copyright © 1996, 2001, 2002 Donnamaie E. White

• Table of Contents
  
• Preface
  
• Overview
  
• Chapter 1 Introduction
  
• Chapter 2 Structured Design Methodology
• Chapter 3 Sizing the Design
• Chapter 3 Appendix = Case Study in Sizing a Design
• Chapter 4 Design Optimization
• Chapter 5 Timing Analysis for Arrays
• Chapter 6 External Set-up and Hold Times
• Chapter 7 Power Considerations
  • Introduction
  • Cell Types Define the Power Computation
  • DC Power in a Bipolar Array
  • DCPower in a BiCOMS Array
  • Overhead Current
  • DC Power in a CMOS Array
  • TTL Outputs - CMOS Arrays
  • ECL Static Output Power - All Arrays
  • AC Power
  • Worst-Case Power
  • Adjustment Multiplier for DC Power
  • Checking with the Vendor
  • Power Reduction Techniques
  • The Macros and Their Options
  • Macro Option Examples
  • Design Rules for Macro Options
  • Power-Down and Conditional Geometry - Bipolar
  • Terminated Outputs - Bipolar
  • Terminated Outputs - BiCMOS, CMOS
  • Inverted Outputs for Distotion Management
  • Design Rules for Power Reduction (AMCC)
  • Unused Inputs - Bipolar, BiCMOS
  • MSI and High-Functionality Macros
  • State Dependent Current - Bipolar
  • Computing DC Power Dissipation
  • Steps to Compute Maximum Worst-Case DC Power
  • Reduction for Single-Supply Circuits
  • CMOS and BiCMOS Arrays
  • Design Rules when Power is to be estimated
  • AC Macro Power Dissipation
• Case Study: DC Power Computation
• Case Study: AC Power Computation
• Chapter 8 Simulation
• Case Study: Simulation
• Chapter 9 Faults and Fault Detection
• Chapter 10 Design Submission
• ASIC Glossary
  • Glossary A-D
  • Glossary E-K
  • Glossary L-R
  • Glossary S-Z
  • Symbols

Power Considerations

Last Edit July 22, 2001

Design Rules for Power Reduction (AMCC)

• Check the library for either power-down of unused outputs or the existence of different output pin versions of the macros. Examine both power and speed differences of these versions
• Minimize the number of terminated outputs
• When a version of a macro is absent from the library, the array vendor may be able to supply a custom macro or an alternate design solution. Do not hesitate to consult the array vendor.

Unused Inputs - Bipolar, BiCMOS

Macros with unused inputs may be dissipating more current than is required for the function being performed. When too many macro inputs are grounded (global ground) or clipped to VDD or VSS, a check should be made to see if another macro could be used that more closely reflects the circuit requirements

MSI And High-Functionality Macros

Dense bipolar macros, as represented by the AMCC MSI macros and any complex chip-efficient macro in any other libraries, represent high-power. They concentrate operations in a small chip area. Their placement in a bipolar array may need to follow row and quadrant current limits. In their favor, their use reduces the number of macros needed to implement a function but the overall current usage may or may not be reduced

BiCMOS MSI macros are generally spread out over a larger number of cells than their bipolar counterparts and do not require the same power considerations

Driver macros on bipolar arrays supply high-drive capability in a small chip area and have the same potential restrictions as for the bipolar MSI macros. The bipolar array may have internal current limits that need to be honored. Drivers reduce the number of other macros that would be required but their use may increase the overall power required by the circuit. High-fan-out drivers were specifically developed for use in clock distribution schemes

Copyright @ 2001, 2002 Donnamaie E. White, White Enterprises
For problems or questions on these pages, contact [email protected]