Logic Design for Array-Based Circuits

Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc.

• Table of Contents
• Preface
  
• Overview
  
• Chapter 1 Introduction
  
• Chapter 2 Structured Design Methodology
• Chapter 3 Sizing the Design
• Chapter 3 Appendix = Case Study in Sizing a Design
• Chapter 4 Design Optimization
• Chapter 5 Timing Analysis for Arrays
• Chapter 6 External Set-up and Hold Times
• Chapter 7 Power Considerations
• Case Study: DC Power Computation
• Case Study: AC Power Computation
• Chapter 8 Simulation
  • Introduction
  • Simulators - The Tools
  • Non-Native Simulators
  • AMCC's Race Check
  • Timing Verifiers
  • Hardware Emulators
  • Golden Simulators
  • Design Validation
  • Wafer Sort/Packages Part Sort Functional Simulation
  • Fault-Grading
  • Testability Analysis
  • Simulation Rules
  • At-Speed Simulation for Timing Verification
  • AC Tests
  • Parametric Vectors
  • Gate Tree - Any Circuit
  • Hazards
  • Structural Hazard Types
  • Functional Hazards
  • What is Required to Fix Race Problems
  • Exercises
• Case Study: Simulation
  • Introduction
  • The Schematic
    • Output Enable
    • Clock
    • MUX Enable
    • Design Checks
    • Annotation
  • The Simulations
    • Functional Simulation
    • Parametric Simulation
    • At-Speed Simulation
    • AC Test
  • Exercises
• Chapter 9 Faults and Fault Detection
• Chapter 10 Design Submission
• ASIC Glossary
  • Glossary A-D
  • Glossary E-K
  • Glossary L-R
  • Glossary S-Z
  • Symbols

Simulation

Last Edit July 22, 2001

AC Tests

Array vendors are beginning to incorporate thermal diodes and AC speed monitors within the base array or as macros that can be added to allow thermal and speed measurements. AC tests may also be allowed, regardless of the presence of a speed monitor.

An AC test is a measurement of one path, input to output, using a single input, a rising or falling signal on that signal, one output and the rising or falling edge on that signal. The vendor may allow set-up and hold measurements or the designer may be restricted to propagation path tests only.

Parametric Vectors

Quality Assurance departments will generally require that the DC parametric tests for VIH and VIL be performed on the array. Should this option be selected, there are several approaches that can be used to ensure proper vectors and conditions for these tests.

The easiest method has been to allow the tests to be made using the test vectors written to perform wafer sort. This approach is acceptable if the inputs to be tested are toggled within the a single page of the vectors; if the input to output paths are combinatorial and if the number of outputs which toggle during those vectors is within the tester limits.

Different vendors may suggest or require alternative approaches. When it is not possible to meet the restrictions that would allow parametric testing with the wafer sort vectors, a successful approach is to add combinatorial gates (NAND, AND, NOR or OR) and one output macro. Gate all inputs or all inputs to be tested through this combinatorial gate tree.

There are several types of inputs that cannot be tested in any of these approaches. They are:

• thermal diodes
• AC monitors
• VBxx macros
• added power
• added ground
• added ECL VCC
• unbuffered ECL inputs
• unbuffered TTL inputs
• three-state enable-drivers

Differential inputs always operate as a pair and each pair should be considered as a single entity when reading the following test methodology descriptions.

Gate Tree - Any Circuit

This approach for parametric testing is the best for any circuit, any I/O mode. It requires internal logic cells, internal routing, and one additional I/O cell.

• If SET or RESET is one signal, start the vector set with the set or reset in the inactive or disabled state (outputs unknown). The second vector will SET or RESET the circuit. This is the only vector that will encounter multiple outputs switching.
• Enable the TEST mode in the first vector if the design requires it. Set all bidirectional macros to the input mode, set up gating, etc. Complete initialization before beginning the parametric test.
• Gate all inputs (except those already identified as exclusions) together (use an AND tree, a NOR tree, etc., as required).
• Bring the result of the GATE tree out to a primary output which must be listed in the simulation vector format. (Note: The parametric tree output will be listed in all simulations performed on this circuit.)
• Identify the gate tree output signal.
• The tree output may be passed through a multiplexor to allow use of an existing primary output only if the circuit is I/O limited.
• One input may switch per vector in the following manner.
  • Start with all inputs at logical "1"
  • Switch one input to "0"
  • Switch that one input back to "1"
  • Switch the next input in sequence to "0"
  • Continue until all inputs have been toggled
  • The gate tree output signal toggles each vector or the reverse (start at "0" and switch to "1" and back).

The toggle pattern of the parametric test is the Minimal Test Sequence for the gate tree. [The Minimal Test Sequence is discussed in Chapter 9.] The Minimal Test Sequence will cover all possible faults in the gate tree. Wafer sort vectors and parametric vectors taken together determine the fault grade score of the vector set for the entire circuit.

Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc.
For problems or questions on these pages, contact [email protected]