Logic Design for Array-Based Circuits

Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White, WhitePubs Enterprises, Inc.

• Table of Contents
  
• Preface
  
• Overview
  
• Chapter 1 Introduction
• Chapter 2 Structured Design Methodology
• Chapter 3 Sizing the Design
• Chapter 3 Appendix = Case Study in Sizing a Design
• Chapter 4 Design Optimization
• Chapter 5 Timing Analysis for Arrays
  • Introduction
  • Path Propagation Delay Overview
  • Intrinsic Set-Up and Hold Time
  • Intrinsic Recovery Time
  • Set-up, Hold and Recovery Specifications
  • Maximum Operating Frequency; Toggle Frequency
  • Intrinsic Pulse Width
  • Interconnect Delays
  • Types of Extrinsic Loading
  • Annotation
  • Manual Computation - One Method
  • Example Equations for Extrinsic Loading - Internal Nets
  • Lnet - Front Annotation
  • Fan-In
  • Fan-Out - Lfo
  • WireOR - Lwo
  • k-Factors
  • Computing Lfo
  • Computing Lwo
  • Computing Lnet
  • Exercises
  • Example Equations for Extrinsic Loading - Output Nets
  • Q5000 Example (Front-Annotation)
  • Worst-Case Delay Multiplication Factors
  • Exercises
  • Front Annotation
  • Remedial Steps - When a Path is too slow
  • Intermediate Annotation
  • Remedial Steps - Intermediate Annotation
  • Back Annotation
  • Remedial Steps - Back-Annotation
  • Exercises
• Chapter 6 External Set-up and Hold Times
• Chapter 7 Power Considerations
• Case Study: DC Power Computation
• Case Study: AC Power Computation
• Chapter 8 Simulation
• Case Study: Simulation
• Chapter 9 Faults and Fault Detection
• Chapter 10 Design Submission
• ASIC Glossary
  • Glossary A-D
  • Glossary E-K
  • Glossary L-R
  • Glossary S-Z
  • Symbols

Timing Analysis for Arrays

Last Edit July 22, 2001

Computing L_fo

Compute L_fo by adding the sum of the electrical loads of all loads driven. If a destination pin has a fan-in of 2, it counts as two electrical loads and as one physical pin. A destination may appear to have two physical loads internal to the macro. In these cases, the macro documentation will clearly identify the fan-in load represented by that pin. BiCMOS libraries have a higher average fan-in than do bipolar libraries.

Computing L_wo

Compute L_wo by multiplying the wire-OR load factor by the size of the wire-OR. For libraries that do not allow a wire-OR, this term becomes zero.

Example: For the AMCC Q5000, WIREOR4 = 1.2 loads.

Computing L_net

For a non-RC tree, non-distributed estimate of metal delays, use the vendor-supplied equation to find the metal loading.

The cell sizes on the larger arrays in the same family are the same as for the smaller arrays. Since the distance from edge to edge of the array is larger, the average distance for an interconnect is larger. Therefore, the same macro path would be estimated as longer on the larger array than on the smaller one. Note that this is strictly the estimate - the actual delay will depend upon the macro positions and the actual routing paths.

Example

AMCC uses:

where (net size - 1) is the physical pin count of the loads driven plus the number of sources on the net (assuming a wire-OR) minus one. When there is no wire-OR, (net size - 1) reduces to pins driven.

Q2000 Series a and b factors (Historical)

For the Q5000, b = 0.67 and a varies by array. The Q5000T uses a = 3.84 and the Q1300T uses a = 1.96. For a macro driving a net sized 8 (net size - 1 = 7), this converts to 14.14 load units for the Q5000T and 6.63 load units for the Q1300T.

Exercises

1. For a Q5000T array, using the above information, what is the typical estimated delay in a net that is driven by a standard macro, if it is sourced by a four-input wire-OR (all sources are standard macros), and drives four other macros each of which has a fan-in of 1?

   Answer:

   k-factor = 0.04 ns/LU rising or falling
   L_wo = 1.2 LU
   L_fo = (4 macros * (fan-in = 1))
   = 4 LU
   L_net = 3.83 * (8-1)** 0.67
   = 14.14 LU
   t_exint = 0.04 * ( 4 + 14.14 + 1.2 ) ns
   = 0.77 ns

2. Repeating for the Q13000T array:

   Answer:

   k-factor = 0.04 ns/LU rising or falling
   L_wo = 1.2 LU
   L_fo = (4 macros * (fan-in = 1))
   = 4 LU
   L_net = 1.96 * (8-1)** 0.67
   = 6.63 LU <== Only difference
   t_exint = 0.04 * ( 4 + 6.63 + 1.2 ) ns
   = 0.46 ns

    

Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc.
For problems or questions on these pages, contact [email protected]