Logic Design for Array-Based Circuits

by Donnamaie E. White

Structured Design Methodology

Review of the Available Arrays

The arrays available at the time of a design evaluation need to be reviewed using the outline in Table 2-3 as an initial basis of comparison.

Table 2-3 Array Checklist - Initial Review

Initial Review Checklist
technology
I/O resources - number of available I/O pads and pins
internal density or equivalent gate limits
I/O mode configurations including power supplies supported
Placement support, options
power dissipation limits
available packaging
maximum operating frequencies internal toggle frequencies interface toggle frequencies
design support: EWS libraries - the macros available Netlister - the macros available annotation support design-correctness software user-friendly interface with test
turnaround time from design submission to wafer prototype
cost

Figure 2-1 indicates the interdependencies between functional specification, hardware specification and the arrays.

Figure 2-1 The Array Selection Process

This review must compare what is available with the circuit specifications and produce a list of the available arrays that could be used to support those specifications. As the number of potential arrays is reduced, preliminary implementations of some of the critical paths for the circuit, constructed from the macro libraries under consideration, should be evaluated.

Historical Table of Commercial, Military Libraries, Power Supplies for One Array Series