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S
- Schematic
- Logic symbol design. Macro symbol representation of the design. Also
refers to blueprints created by other means.
- Schematic capture
- The process of entering macros and their interconnections into an
EWS before error analysis and simulation.
- Semicustom array
- An array that is pre-designed in all base levels, leaving the top
n levels for user-defined connections.
- Series, as in logic array series.
- Devices that are similar, differing in size; a related set of products.
- Series gating
- Transistor chaining.
- S
- Set Q output of a latch or flip/flop to TRUE, usually = 1.
- Signal pin
- A pin carrying a variable signal rather than power or ground. This
is also used as an abbreviation for package signal pin.
- Silicon compiler
- Software that translates a circuit description at the behavior or
gate level to a pattern generator tape.
- Simulation vector
- A bit-pattern used to evaluate functionality, parametrics, or timing
performance of a circuit or array.
- Single-ended input
- Single rail One polarity (as opposed to differential input).
- Skew
- The amount of variation in propagation delay between two logical gates.
A function of placement, switching, whether the two gate functions are
on identical macros, on the same power bus, have the same loading, etc.
- Speed/power ratio
- Term used to indicate the tradeoff of higher speed for higher current
and therefore power dissipation.
- SSI
- Small Scale Integration; 2-20 equivalent gates on a chip; AND, OR,
NOT level gates.
- Stabilization time
- Time required for a circuit to reach a stable, known state.
- Standard cell
- An approach to customization in which all mask levels (as many as
14) are stored with a macro. The base wafer is not made ahead of time.
Tooling costs are higher than with semi-custom gate arrays. Debug takes
longer than for semi-custom. Depending on the designer, it may save
die area and therefore overall cost for large production runs. Differences
between it and gate arrays are in reality slight and die costs are not
the leading expense.
- Standard macro
- The basic parametric configuration for a macro. All macros have an
S-option although drivers have only one option.
- SWGROUP
- A macro parameter that allows the user to "tag" members of a switching
group (simultaneously switching outputs).
T
- Testability Analysis
- Evaluation of the controllability and observability of a circuit.
Controllability is the measure of how easy it is to toggle a node. Observability
is the measure of whether the toggling of a node can be seen at an output
easily, with difficulty, or not at all.
- Thermal diode
- Constructed from input and output macros with a choice of sizes (2X
transistor normally used), this device allows thermal measurements to
be made for a device. A thermal diode is incorporated into the base
for the Q20000 Series arrays.
- Three-level gating
- Three-stage transistor staging; proprietary technique used in the
earlier AMCC Q3500 and Q5000 Series Bipolar Logic Arrays.
- Trench-oxide isolated
- Technology used in the bipolar high-speed AMCC Q20000 Series (1.2GHz).
- TTL
- Transistor-Transistor logic, AKA T2L.
- TTL
- output drive See IOL
- Turbo driver
- An AMCC-patented dynamic discharge circuit that replaces the static
current source of the emitter follower. This allows lower power, higher
drives, and reduced skews.
U
- Uncommitted logic
- Logic whose use or application is not predetermined by the manufacturer.
V
- VHDL
- VHSIC hardware description language, a high-level design language.
- VHSLSI
- Very high-speed large scale integration. See VHSIC.
- VHSIC
- Very high-speed integrated circuits, from the American military program
(Department of Defense).
- VLSI
- Very large scale integration, over 1000 equivalent gates, (1000-10000
gates on a chip).
W
- Wafer
- The silicon slice (various diameter circles) upon which multiple layers
of doped materials have been placed to form a number of usable component
chips known as dice. Yield is usually stated as the number of usable
die per wafer. Wafers consist of layers of conducting, partially conducting
and non-conducting materials. The layers form active and pas-sive components
of the die.
- Worst-case COMMERCIAL
- Refers to the multiplication factors used to compute maximum worst-case
power and maximum worst-case path propagation delay when the circuit
is for COMMERCIAL application. Or, refers to the worst-case maximum
specifications under Commercial operating conditions.
- Worst-case MILITARY
- Refers to the multiplication factors used to compute maximum worst-case
power or maximum worst-case path propagation delay when the circuit
is for MILITARY application. Or, refers to the worst-case maximum specifications
under Military operating conditions.
- Worst-case multiplier
- The adjustment factor specified for use in computing maximum worst-case
current from typical current specifications, or for computing maximum
or minimum worst-case time delays from typical time delays. Adjustment
factors may be required to adjust for power-supply. Refer to the Design
Manual for the specific array to determine what multipliers are required.
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