Logic Design for Array-Based Circuits

by Donnamaie E. White

Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc.


Sizing the Design - Selecting the Array

Architectural Specification or Hardware Specification

Once a clear definition exists of the circuit or circuits that will be placed on one array, then the planned design can be developed. This is on a smaller module scale than the block-level functional specification, e.g., at the level of counters, adders, latches, registers, sequencers, etc. The performance requirements defined in the functional specification can be used to select the technology.

The review of available arrays is conducted in parallel with the creation of the hardware specification.

With the descriptions developed for the modules, equivalent gate estimates can be made for the circuit, or estimated cell usages can be computed for the circuit on a specific array. The array vendor Applications Engineer can help with the sizing esti mate.

The hardware design specification details what the designer intends to do to meet the target functional specification. This level of specification can be equated to a PDL (program definition language) description of software and is the basis for the evolution of HDL, hardware description language, and its derivatives.

If a particular testing methodology is being enforced, the sizing estimates must take this additional logic into account. If additional testing logic, such a parametric gate tree or parity logic, is to be used, it must be included in the sizing estimates.

The specification may include proposed vendors and arrays.

Table 3-6 Components of The Hardware Specification

Hardware Specification Components
The selected technology or technologies
Potential array series (1-3 at the most)
Block level diagram to the sub-module level
The functional description of the different circuit sub -modules such as adders, counters, registers, etc.
Sub-module sizing
--- equivalent gates or estimated internal cell utilization
--- estimated I/O cell utilization
--- estimated pad utilization
--- estimated internal pin counts
Refined details on the array interface
--- number of CMOS I/O
--- number of TTL I/O
--- number of ECL 10K I/O
--- number of ECL 100K I/O
--- all four types partitioned into inputs and outputs and bidirectionals
--- number of outputs switching simultaneously (by type) (SSOs)
--- maximum toggle frequencies for each I/O
--- external set-up and hold window unless this circuit will establish the window specification for the driving circuit
Critical path throughput performance
Estimated power - DC and AC as required
Package to be used
Heatsinks required and/or air cooling required
Estimated junction temperature

There should be a design review of the architectural or hardware specification before final selection of an array series. On final selection, the specification should be revised to show that series and all computations performed for that series.

Note: a workstation provided some assistance. The critical path may be captured in more than one version and comparisons made based on an annotated simulation.

You can do the same thing with RTL - trying different solutions to tricky parts of the circuit - looking for the best solution.

Power and sizing details can be run against a macro list rather than a full interconnect netlist. (This tool is vendor-dependent.) Check if such a pre-capture tool is available to help size the circuit.


Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc.
For problems or questions on these pages, contact donnamaie@-no-spam-sbcglobal.net