Logic Design for Array-Based Circuits
Structured Design Methodology
Compute the Path Propagation Delay
Compute the path propagation delay for the most critical (time sensitive) paths in the circuit. Make adjustments to the schematic in terms of macro options for speed where needed. Does the estimated performance satisfy the specification?
For the arrays that use typical specifications, be certain to use the correct multiplication factor (WCM) for this worst-case analysis. Review the assumptions made in establishing the multiplication factors and adjust them if these assumptions are not expected to be met (i.e., derate the performance by a higher factor). Some vendors call these multiplication factors "adjustment factors". Be clear as to what is being adjusted and why.
There may be different multipliers for the different product grades, Commercial and Military, and for different power supplies within the product grade. The multiplier may depend on the macro type.
Many arrays are specified without worst-case timing multipliers. They are specified with min/max ranges for each macro propagation delay. Maximum path delay is found using the MAX data although the conditions for a maximum propagation delay for an individual macro will vary. Minimum delays are found using the MIN data.
Be certain that the proper fan-out loading and performance specifications are selected when doing this computation. Because of the high degree of variation in the way a library is documented between vendors and between array series from the same vendor, be certain that the rules regarding the methods of specifying timing delays for the macros for the array series selected are clearly understood.
Internal extrinsic loading delays are composed of metal load (Lnet), electrical fan-out load, the sum of all loads driven (Lfo), wire-OR electrical loading if the array allows wire-ORs and if one was used in the net (Lwo) and the k-factors for each. The k-factors, expressed in ns/LU, convert the load units into time units. Table 2-7 shows the extrinsic load equations for internal nets as they are used by AMCC and other vendors. K-factors may be specified as tables, graphs, or broken down into parts for temperature, voltage and processing. Check with the specific vendor.
Table 2-7 Components Of Path Delay - Internal Loading
External extrinsic loading delays are composed of the system load capacitance and the package pin capacitance (Lcap) and the k-factor. The k-factor, expressed in ns/pF, convert the load capacitance into time units. The equation used by AMCC for this delay are listed in Table 2-8.
Table 2-8 Components Of Path Delay - External Loading
All this became moot when first RTL (VHDL then Verolog) came into being followed by Design Compiler and Design Analyzer, and then PrimeTime STA software. Static Timing Analysis tools compute the timing, find the worst-case path, examine set-up and hold, compute path propagation delays, worst case (if you tell them to), etc. and took over the tedious and error-prone methods those of us who designed in the bipolar array era pre-RTL had to perform by hand.
Understanding the methodology however is still valid, and allows today's designer to understand just what is being computed by these EDA software tools. Too often, the designer runs them, but doesn't "get" them.