Logic Design for Array-Based Circuits

by Donnamaie E. White

Sizing the Design - Selecting the Array

Review the Available Arrays

With a clear understanding of the design description and overall objectives, review the arrays currently available that could be used.

For a listing of currently-available array series, check with the latest ASIC vendor surveys run by several of the engineering magazines. These buyer's guides provide a cursory look at what is available and allow a first-pass sort of available arrays into feasible and non-feasible, a staring point from which the designer can proceed. They have limited space to review technology, die size, cell counts, metal layers, number of macros, interface levels, second sources and the EWS workstations the array ven dor supports. They may not have the latest updates on an array series. They can provide addresses and phone numbers for array vendors.

Once one or more vendors have been selected, the designer should obtain data sheets and design guides from the prospective vendors for the most promising array series and begin a more in-depth review.

Example - The AMCC Arrays - as of 1991

The industry shows an evolutionary trend as designers drive them to develop larger, faster and cooler arrays.

There have been five bipolar array families from AMCC since 1984, (see Table 3-2) increasing in cell size and speed while reducing die size and power. The most recent is the AMCC Q20000 series, officially released in September 1989.

Table 3-2 AMCC Bipolar Array Series

AMCC Array Series	Year
Q20000	1989
Q5000	1987
Q3500	1986
Q1500	1985
Q700	1981

The Q20000 Series speed estimates list its internal toggle rate, at least twice as fast as that of the previous Q5000 Series, at 1.25GHz, with an enhanced drive and much lower power. Individual macros have been found to run at 1.4GHz and higher.

There are two AMCC BiCMOS array families, the Q14000 Series and the Q24000 Series, a partial shrink of the Q14000, as shown in Table 3-3.

Table 3-3 AMCC BiCMOS Array Series

AMCC Array Series	Year
Q24000 Series	1990
Q14000 Series	1988

The current BiCMOS families were preceded by three CMOS array series, each faster than its predecessor. The BiCMOS arrays combine the drive and interface ability of bipolar with the cooler operation of CMOS. The newer BiCMOS Series must be larger, faster and cooler.

Comparing the arrays

The items that define the differences between array series include those shown in Table 3-4.

Table 3-4 Features for Array Series Comparison

Array Series Comparison Topics
The process technology
Metal layers routed (2, 3)
Series gating techniques
Sea-of-cells versus routing track architectures also called channelless vs. channelled
Overall Maximum Speed of Operation specified as I/O and internal toggle rates
Frequency Ft (frequency at which beta for transistor becomes unity)
Noise immunity
Edge rates - programmable or not
Symmetry in rise and fall times
Power-supply options allowed
Power-supply variation stability
Maximum number of I/O cells available
I/O modes allowed (TTL, ECL, MIXED, etc.)
ECL terminations
On-chip translators
Maximum number of internal cells or gates available
Features for Array Series Comparison
Macro Options - Standard (S); Power (P); Low-power (L); High-speed (H); Fast (V), Drivers (D); super-drivers (D)
- - - or lack of options; i.e., speed-power programmability
Variety in the macro library available
Wire-ORs (dot-wire) allowed or not
Design constraints
Power dissipation per gate
Packaging Available
Autoplace, Autoroute
Engineering Workstation support
Simulators supported
Second source
Military compatible
Commercial compatible
Military qualified testing
Other topics as dictated by the arrays, their technology and the design issues

The arrays within a series refine these differences with specific information on size, number of cells by type, and details about interfacing, as shown in Table 3-5.

Table 3-5 Array-Specific Specifications

Number of Internal Cells (size of the core area)

Number of I/O Cells

Number of Outputs

Number of Bi-Directional

Number of Fixed Power and Grounds

Rules for Adding Power and Ground

Packaging Options

Maximum Internal Current Limits

On-Chip Memory

Macro-type Design Limits - such as Darlington, CML outputs

Placement Rules and Restrictions that Affect / Restrict Design

Variable Bonding

Data sheets, product profiles and macro library design guides or design manuals supply the specific information for an array series. The design manual, supplied with the array library media, is the controlling document.

Most of the above would come from the technology array and process vendor. This vendor supplies the base die design and the basic macro library. While packaging and the final die size are up to the designer (and the marketing specification and requirements document), all physical rules still must be known and considered today. We don't use a pre-sized array, but we must allow for the same added power/ground requirements, power limitation, and basic design rules. We also use CMOS arrays, not bipolar. Interesting enough, 85% of the design rules are identical between bipolar and CMOS, the greatest difference is in the way power is computed and restricted.

The AMCC ASIC Product Selection Guide for the Q20000 Series of Arrays

AMCC ASIC PRODUCT SELECTION GUIDE

(1990's)

Part
Number Technology Equivalent
Gates
(Full Adder
Method) Number
of I/O Structured
Array Blocks

Q20004 1 Micron Bipolar 671 28 None

Q20010 1 Micron Bipolar 1469 66 None

Q20025 1 Micron Bipolar 4032 100 None

Q20045 1 Micron Bipolar 6782 128 None

Q20080 1 Micron Bipolar 11242 162 None

Q20120 1 Micron Bipolar 18777 198 None

Q20P010 1 Micron Bipolar 928 34 1 GHz PLL

Q20P025 1 Micron Bipolar 3120 51 1 GHz PLL

Q20M100 1 Micron Bipolar 13475 195 RAM

Believe it or not, people are still trying to design with the Q20000 series - they need to build replacement arrays as older chips wear out.