Logic Design for Array-Based Circuits

by Donnamaie E. White

Design Optimization

Last Edit July 22, 2001

Design to Improve Speed

If a macro library provides speed-power options for the macros available, an initial design is done selecting the standard macro options (the middle choice) and is also done from the perspective of logic minimization. Once the array technology has been selected, circuit speed is affected by the major factors shown in Table 4-3.

Table 4-3 Designing To Improve Speed

Optimize for Speed
Review the macro chosen Review the macro option Review Macro functionality Perform Logic minimization Reduce the fan-out loading Reduce wire-OR loading (if allowed)

In the case study, the change of the output macro to allow the circuit to operate at specification did not affect cell count and reduced the power by three Watts.

The solution of timing problems are not often so simplistic or beneficial. When faced with a circuit that does not meet timing specifications, changing macros can lead to increased cell counts, no change or decreased cell counts and higher power dissipation, no change or a reduction in pow-er dissipation.

Macro options

When an array provides macro options, those options should be reviewed for applicability to the design problem. If a macro comes in low-power, high-speed and standard options, they will each have a different toggle frequency or maximum frequency of operation. Each option may have a different fan-out load or drive capability. Each option will have a different power dissipation. In some case, the different options may have different cell counts.

The selection of a high-speed macro option may carry power dissipation penalties that may in turn lead to other macros needing to be downgraded to low-power options. This may be necessitated by an internal current limit for the array or from the early estimates of the junction temperature. As long as the toggle frequency of the low-power macros are not violated and the fan-out load limits are not exceeded, then the use of low-power options is acceptable.

When a library has driver macros with balanced load delay drive factors (minimal skew) and faster intrinsic (internal) delays, the use of the driver should be justified. Drivers typically carry a power dissipation penalty. They should be used in clock distribution lines and for heavily loaded paths that have tight timing specifications.

Macro functionality

Another reason to review the macro library before finalizing a design is that speed is usually a function of density. In general, a high-functionality multiple-cell macro will perform better than a circuit module formed from equivalent macros. Intra-macro nets (connecting components) are shorter than inter-macro interconnect delays.

A hard macro, where the routing is always in the same pattern, can guaranty its worst-case speed. A soft macro has placement require ments and priority routing that must be used if it is to meet its specifications.

High-functionality macros also include those that combine functions, such as the 3:1 MUX-D flip/flop macros (supporting testing), dual flip/flops, triple latches or triple multiplexors, internal-I/O dual function macros that ensure the maximum utilization of the complex I/O cells, or combined two-cell bidirectional-added ground macros, that keep the second pad from being wasted. High-functionality macros are those that prevent or minimize wasted (unused) silicon, pads or cells.

Other design techniques to increase the circuit density include replacing gate structures with multiplexors where the speed and gate count would be reduced. (See Digital Design with Standard MSI and LSI, 2nd ed., by T.R. Blakeslee, 1979, Wiley, New York.)