Logic Design for Array-Based Circuits - D. E. White - eBook


Logic Design for Array-Based Circuits by Donnamaie E. White Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc.

Table of Contents Preface Overview Chapter 1 Introduction Chapter 2 Structured Design Methodology Chapter 3 Sizing the Design Chapter 3 Appendix = Case Study in Sizing a Design Chapter 4 Design Optimization Chapter 5 Timing Analysis for Arrays Chapter 6 External Set-up and Hold Times Chapter 7 Power Considerations Case Study: DC Power Computation Case Study: AC Power Computation Chapter 8 Simulation Introduction Simulators - The Tools Non-Native Simulators AMCC's Race Check Timing Verifiers Hardware Emulators Golden Simulators Design Validation Wafer Sort/Packages Part Sort Functional Simulation Fault-Grading Testability Analysis Simulation Rules At-Speed Simulation for Timing Verification AC Tests Parametric Vectors Gate Tree - Any Circuit Hazards Structural Hazard Types Functional Hazards What is Required to Fix Race Problems Exercises Case Study: Simulation Introduction The Schematic Output Enable Clock MUX Enable Design Checks Annotation The Simulations Functional Simulation Parametric Simulation At-Speed Simulation AC Test Exercises Chapter 9 Faults and Fault Detection Chapter 10 Design Submission ASIC Glossary Glossary A-D Glossary E-K Glossary L-R Glossary S-Z Symbols	Simulation Last Edit July 22, 2001 Hazards Timing checks in the simulators are designed to help the designer screen hazards and race conditions from the circuit and from the test vector set. LASAR 6 is used as the role model for race and hazard evaluation. Timing hazards are divided into two basic categories: structural and functional. Structural Hazard Types * Converging Ambiguities A Convergence hazard is one where at least two edges come together at a primitive and the ambiguity associated with the edges overlap so that the primitive may or may not pulse. (A primitive is an element provided by the simulator software. It is a basic building block used to construct a logic model.) * Cumulative Ambiguity A primitive in the model has a pulse at its output, but the ambiguities at the rising and falling edges are so large that they overlap. Since the whole pulse is "gray", it may or may not occur and is therefore flagged as a hazard. * Composite Hazard A primitive's inputs change in such a way that the primitive's output will change at a future time. If, before that time occurs, the inputs change again in such a manner that the output change would be reversed, then the simulator doesn't know if the primitive output will respond at all. (This can be described as the inputs changing faster than the propagation delay of the primitive.) This is flagged as a hazard by LASAR 6. Functional Hazards * Setup violations Set-up time violations are situations where a node has not remained in a stable state long enough before another node changes state. This test is common on data inputs to flip/flops with respect to the clock of the flip/flop. * Hold time violations Hold time violations are situations where a node does not remain in a stable state long enough after another node changes state. This is common on data lines with respect to clock inputs where the data must be maintained in a stable state for a specified time after the clock change. * Minimum pulse width violation The time between two consecutive edges of a signal must be greater than a specified value. * Minimum period violation The time between two consecutive rising or falling edges of a signal must be greater than a specified value. For a node that has multiple hazards associated with it within a single pattern, only the last hazard is reported by LASAR 6. The resulting hazard report file will contain only those hazards that meet the definition of "persist". A persistent hazard is one that causes a node to go unknown and stay unknown until the end of the current pattern. This is a valid way of screening out combinatorial glitches so long as the sample time is long relative to the longest delay time. What is required to fix race problems * Identify source of problem The above errors can be caused by vector races or by internal timing conditions. The LASAR 6 hazard report file will show a trace back to the primary input or inputs that caused the error. If it is traced to two separate inputs then it can generally be fixed by changing the input pattern as long as it does not violate the intended function. If it is traced to only one input then the problem is due strictly to internal timing and will require modification of the circuit to change its timing. * Implementing The Fixes In the case of a vector race, it will be necessary to return to the EWS system where the design was done. The simulation input file must be modified to fix the timing problem and the simulations rerun. In the case of the internal timing problems, it will still be necessary to return to the EWS system, this time to modify the schematic as required. After this is done, rerun all steps, including all simulations, before returning to RaceCheck. * Looping caused by iterative fixes Iterative fixes may result from three primary causes. If a fix for a previous error introduces a new error then the process will have to be repeated to fix the new problem without going back to the old one. The second cause is due to a hazard causing an entire path to become unknown (X) for an extended time. This leaves the possibility that a node down stream has a hazard that was blocked by the X state existing from the previous upstream hazard. The third, but least common cause, is the fact that the simulator, such as LASAR 6, reports only one hazard at a time for a given node within a single pattern. Exercises Read at least four survey articles in current literature that discuss ASIC simulation, workstations, simulators, timing verifiers and hardware emulators. What trends do these articles show? Select three to ten array vendors. Discover what workstations, simulators, and other support tools are available from these vendors. Do they offer design centers (provide equipment to designers at specific sites)? Read at least two articles on the concept of a "golden simulator". Discuss the impact of this approach on designers used to their own workstations. Select either an 8-bit adder, 8-bit counter or 16-bit multiplexor. Develop 100% fault coverage wafer-sort vectors. The circuits are of your own design as to interface, etc. Write AC propagation path only test vectors for any six paths in the circuit chosen in Exercise 4. Develop a gate-tree and its vector set for the circuit chosen in Exercise 4.
Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc. For problems or questions on these pages, contact donnamaie@-no-spam-sbcglobal.net