Logic Design for Array-Based Circuits

Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc.

• Table of Contents
  
• Preface
  
• Overview
  
• Chapter 1 Introduction
• Chapter 2 Structured Design Methodology
  
• Chapter 3 Sizing the Design
  • Functional Specification - A Closer Look
  • Review the Available Arrays
  • Architectual Specification or Hardware Specification
  • Array Sizing
  • Cell Capabilities
  • Array Architecture
  • Netlist
  • Example: AMCC Interface Options
  • Example - AMCC Arrays - Power Supply Options
  • Interface Cell Functionality
  • Examples
  • Internal Cell Functionality
  • Multi-Cell Macros
  • Hard and soft macros
  • Refining Interface Requirements
  • Adding Extra Power and Ground Macros
  • Dual-Function I/O Macros
  • Example - Simultaneously Switching Outputs
  • Thermal Diodes
  • The AMCC Speed Monitor
  • Final Interface Cell Utilization
  • Drivers
  • Exercises
• Chapter 3 Appendix = Case Study in Sizing a Design
• Chapter 4 Design Optimization
• Chapter 5 Timing Analysis for Arrays
• Chapter 6 External Set-up and Hold Times
• Chapter 7 Power Considerations
• Case Study: DC Power Computation
• Case Study: AC Power Computation
• Chapter 8 Simulation
• Case Study: Simulationest
• Chapter 9 Faults and Fault Detectiond Output
• Chapter 10 Design Submission
• ASIC Glossary
  • Glossary A-D
  • Glossary E-K
  • Glossary L-R
  • Glossary S-Z
  • Symbols

Sizing the Design - Selecting the Array

Exercises

1. Select a semi-custom array series (any).
List:

• the processing technology
• available power supply configurations
• types of TTL input and outputs allowed
• types of ECL input and output allowed
• how bidirectional macros are handled

2. For the selected series, what cell usage restrictions exist?

• a. Any limits on inputs
• b. Any limits on outputs
  • TTL
  • ECL
• c. Any limits on bidirectionals
• d. Any rules for simultaneously switching outputs
• Are the rules easy to find?

3. For the selected series, how many fixed power and ground pads are on each array in the series? How are additional power and ground pads added?

4. For the selected series, what types of cells are available on each array and how many of each type?

5. How many internal cells would be required by the selected array series macros to implement an 8-bit barrel shift register (8 2:1 MUXs with 8 4:1 MUXs, 8 D flip/flops)?

6. Given a 16-bit fast adder design using carry-look ahead, 16 DATAA and 16 DATAB inputs, necessary controls (clock, reset, carry-in), a registered output, 17 outputs (sum plus carry out), size the design for the macro library for the selected array series. Assume a COMMERCIAL environment, single -5.2V power supply, ECL is ECL 10K or ECL 10KH.

Fast adder: four 4-bit fast adders with carry-propagate outputs; one 4-bit carry-look ahead unit; 17 D flip/flops; 35 ECL inputs; 17 outputs; buffers and gates as required; added power/ground as required.

7. Given a 32-bit register, 35 ECL inputs (32 data, clock, reset, 3-state enable), dual ECL-TTL outputs (32 TTL 3-state and 32 ECL, same signals), size the design for the selected array series. Assume a MILITARY environment, dual-power supplies of +5V and -5.2V, ECL is ECL 10K or ECL 10KH.

Register: 32 D flip/flops, 35 ECL inputs; 64 ECL outputs; buffers and gates as required; added power and ground as required.

Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc.
For problems or questions on these pages, contact [email protected]