Logic Design for Array-Based Circuits

Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc.

• Table of Contents
  
• Preface
  
• Overview
  
• Chapter 1 Introduction
• Chapter 2 Structured Design Methodology
  
• Chapter 3 Sizing the Design
  • Functional Specification - A Closer Look
  • Review the Available Arrays
  • Architectual Specification or Hardware Specification
  • Array Sizing
  • Cell Capabilities
  • Array Architecture
  • Netlist
  • Example: AMCC Interface Options
  • Example - AMCC Arrays - Power Supply Options
  • Interface Cell Functionality
  • Examples
  • Internal Cell Functionality
  • Multi-Cell Macros
  • Hard and soft macros
  • Refining Interface Requirements
  • Adding Extra Power and Ground Macros
  • Dual-Function I/O Macros
  • Example - Simultaneously Switching Outputs
  • Thermal Diodes
  • The AMCC Speed Monitor
  • Final Interface Cell Utilization
  • Drivers
  • Exercises
• Chapter 3 Appendix = Case Study in Sizing a Design
• Chapter 4 Design Optimization
• Chapter 5 Timing Analysis for Arrays
• Chapter 6 External Set-up and Hold Times
• Chapter 7 Power Considerations
• Case Study: DC Power Computation
• Case Study: AC Power Computation
• Chapter 8 Simulation
• Case Study: Simulationest
• Chapter 9 Faults and Fault Detectiond Output
• Chapter 10 Design Submission
• ASIC Glossary
  • Glossary A-D
  • Glossary E-K
  • Glossary L-R
  • Glossary S-Z
  • Symbols

Sizing the Design - Selecting the Array

Example: AMCC Interface Options

For all AMCC arrays, TTL and ECL translators are included in the I, O, or I/O cells for external interfacing to both ECL and TTL. Each I, O, or I/O cell can be configured to be either TTL, ECL 10KH, ECL 10K, ECL 100K or as a power or ground pad.

I/O cells can usually be used for input macros, output macros or bidirectional macros. Table 3-12 shows the possible I/O combinations allowed on AMCC arrays while Table 3-13 details the TTL output options and Table 3-14 the ECL output options.

Table 3-12 AMCC Interface Combinations

Table 3-13 TTL OUTPUT OPTIONS

The 3-state outputs and TTL bidirectional macros have an enable pin that is either restricted to being driven by a specific macro type (a 3-state enable driver) or unre stricted and driveable by any internal-level signal. The restriction depends on the array and on the mode (100% TTL or Mixed ECL/TTL) of the circuit.

Table 3-14 ECL Output Options

From CML forward in the above list are types identified as possible for the Q20000 Series. Standard ECL 10K, 100K, CML and Darlington outputs were in the first re lease of the macro library for the series.

Power Supply Options

In addition to the types of interface required, the power supply or power supplies to be used should be compared to the supplies allowed for the array. The supplies, the number of fixed power and ground pads and their locations should be reviewed for their applicability to the design in question.

There is often a need to have an array interface with several types of I/O while keeping power supply requirements in line with what is already provided on the target PCB (printed circuit board). This can lead to operation of a technology with non-standard voltages.

Effects on Parametrics

When non-standard voltages are used, such as -4.5V with ECL 10K and -5.2V with ECL 10K, the DC parametrics for the array will be affected. The data sheet for the array series will call out the parametrics for standard supplies.

The vendor must be consulted for computational procedures to be used when non-standard power supplies are used.

Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc.
For problems or questions on these pages, contact [email protected]