Logic Design for Array-Based Circuits

Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc.

• Table of Contents
• Preface
  
• Overview
  
• Chapter 1 Introduction
  
• Chapter 2 Structured Design Methodology
• Chapter 3 Sizing the Design
• Chapter 3 Appendix = Case Study in Sizing a Design
• Chapter 4 Design Optimization
• Chapter 5 Timing Analysis for Arrays
• Chapter 6 External Set-up and Hold Times
• Chapter 7 Power Considerations
• Case Study: DC Power Computation
• Case Study: AC Power Computation
• Chapter 8 Simulation
  • Introduction
  • Simulators - The Tools
  • Non-Native Simulators
  • AMCC's Race Check
  • Timing Verifiers
  • Hardware Emulators
  • Golden Simulators
  • Design Validation
  • Wafer Sort/Packages Part Sort Functional Simulation
  • Fault-Grading
  • Testability Analysis
  • Simulation Rules
  • At-Speed Simulation for Timing Verification
  • AC Tests
  • Parametric Vectors
  • Gate Tree - Any Circuit
  • Hazards
  • Structural Hazard Types
  • Functional Hazards
  • What is Required to Fix Race Problems
  • Exercises
• Case Study: Simulation
  • Introduction
  • The Schematic
    • Output Enable
    • Clock
    • MUX Enable
    • Design Checks
    • Annotation
  • The Simulations
    • Functional Simulation
    • Parametric Simulation
    • At-Speed Simulation
    • AC Test
  • Exercises
• Chapter 9 Faults and Fault Detection
• Chapter 10 Design Submission
• ASIC Glossary
  • Glossary A-D
  • Glossary E-K
  • Glossary L-R
  • Glossary S-Z
  • Symbols

Simulation

Last Edit July 22, 2001

Output Enable

Where a pin must be driven by another macro or where tying a pin to ground would be unacceptable, the use of another macro that can be tied to ground is required. This circuit uses a static driver that could drive 50 loads. It drives 39 loads in this case.

There are design restrictions and tester limitations that affected the design of an output enable circuit. First, not all outputs may change state during testing (the limit is 16). This has nothing to do with normal circuit operation. To accommodate this vector restriction, test-enable inputs may need to be designed into the enable structure. This circuit did not require any test enables.

Page Two

The control circuitry is grouped on page two. There are three modules, clock, reset and MUX enable. All macros and all external signals are named as are signals that go from one page of the schematic to another.

Naming other internal nets is arbitrary, and usually depends on the need to trace them during critical path analysis.

Vendor-specific rules require that any signal that goes to one or more other pages have those pages noted. Any signal coming from another page must have that page noted. This is part of the human-readability.

Clock

The clock uses library-specific clock drivers. GT55D macros are low skew-high load drivers. They are driven by a differential-macro IE31H. The array-specific rule in use here, since the speed will not exceed 600 MHz, is to derate the fan-out load capability of all macros in the clock net by 40%. On the schematic, this appears as a 40 near the internal signal "INTCLK" and near "ICA", "ICB", "ICC" and "ICD".

The use of a fan-out derating parameter is vendor-specific. AMCC uses FOD attached to a net to derate the pin of the macro driving the net.

Fan-out loading for the clock depends on the macros driven. Regardless of loads driven, it is often desirable to keep the clock lines balanced, in this case placing fewer loads on each driver. Fan-out load derating for clock lines is a typical vendor requirement and you should verify what a chosen vendor will require.

Reset

The reset structure is simple, using eight GT09S standard macros. Fan-out loading for the reset line does not require derating. Each macro output pin will drive 12 loads.

MUX Enable

The 2:1 MUX enable must drive 32 loads so a small buffer tree consisting of two gates was added. To reduce internal cell usage, a high-power driver could have been used.

Page Three

Page three contains the four enables for the 16:1 multiplexors, and the six pass-through inputs and outputs. The outputs use the static driver.

Page Four , Fourteen

Page four and fourteen show the 16:1 MUXs. The output macro is OE42S that does use an output-enable control (from sheet 3).

Page Five through Twelve

Pages five through twelve are identical in macro content except that the names of the macros and signals will be different. Each page is a 4-bit "slice" of the register.

This circuit cannot be drawn using hierarchy due to vendor-specific rules that require all I/O macros to be at the top of the drawing hierarchy. The only non-I/O macros on these pages are the flip/flop macros.

The flip/flops used in the drawing are FF46S and FF10S. Although the flip/flops are in the critical path, the use of 32 H-option flip/flops would make the design very hot.

The 3-input OR/NOR has the C pin tied to ground but the B pin tied to the static driver. The macro requires that B or C be driven by a macro. By sending the flip/flop output into the B or C pin, the remaining pin and the A pin could be tied to ground and the schematic could be simplified. It would also reduce routing nets - an important issue even for channelless arrays.

Note the vendor-specific switching-group parameter "AAA" used on each output macro.

Page Thirteen

The thirteenth page contains a parametric gate tree. The parametric gate tree is a vendor-specific requirement to allow parametric VIH, VIL testing. All circuit inputs are ORed and brought out to one output macro, in this case OE42S. The actual connection is to the output pin of the input macro. When an I/O macro has two output pins, using the otherwise unused pin prevents the actual circuit from "seeing" the time delay imposed by the net driving the gate tree. When no unused pin exists, an added fan-out load will be introduced.

Gate trees are the recommended approach to any sequential circuit with more than 8 simultaneously switching outputs (mixed-mode or TTL/ECL mixed circuit) or 16 (100% TTL or 100% ECL circuit) in any vector.

Design Checks

This circuit passed all design checks - with a warning that perhaps added power macros might be required at placement.

Annotation

The annotation files were generated using a 251_PGA_CD package - 251 pin grid array cavity down. This establishes an estimate for the package pin capacitance for the output macro loading. Annotation was run without incident.

Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc.
For problems or questions on these pages, contact [email protected]