Logic Design for Array-Based Circuits


Logic Design for Array-Based Circuits by Donnamaie E. White Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White, WhitePubs Enterprises, Inc.

Table of Contents Preface Overview Chapter 1 Introduction Chapter 2 Structured Design Methodology Chapter 3 Sizing the Design Chapter 3 Appendix = Case Study in Sizing a Design Chapter 4 Design Optimization Chapter 5 Timing Analysis for Arrays Chapter 6 External Set-up and Hold Times Chapter 7 Power Considerations Case Study: DC Power Computation Case Study: AC Power Computation Chapter 8 Simulation Case Study: Simulation Introduction The Schematic Output Enable Clock MUX Enable Design Checks Annotation The Simulations Functional Simulation Parametric Simulation At-Speed Simulation AC Test Exercises Chapter 9 Faults and Fault Detection Chapter 10 Design Submission ASIC Glossary Glossary A-D Glossary E-K Glossary L-R Glossary S-Z Symbols	At-Speed Simulation - Print On Change - 32-Bit Register Last Edit October 8, 1996 File_name = ../bitregatspdpoc.vec File_type = PRINT_ON_CHANGE Test_type = AT_SPEED_SIMULATION Simulation_type = MAXIMUM Annotation_type = FRONT_ANNOTATION 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Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc. For problems or questions on these pages, contact [email protected]

Logic Design for Array-Based Circuits

by Donnamaie E. White

At-Speed Simulation - Print On Change - 32-Bit Register