Logic Design for Array-Based Circuits - D. E. White - eBook


Logic Design for Array-Based Circuits by Donnamaie E. White Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc.

Table of Contents Preface Overview Chapter 1 Introduction Chapter 2 Structured Design Methodology Chapter 3 Sizing the Design Chapter 3 Appendix = Case Study in Sizing a Design Chapter 4 Design Optimization Chapter 5 Timing Analysis for Arrays Chapter 6 External Set-up and Hold Times Chapter 7 Power Considerations Case Study: DC Power Computation Case Study: AC Power Computation Chapter 8 Simulation Case Study: Simulation Chapter 9 Faults and Fault Detection Introduction Controllability Observability Masking a Fault Fault Types Fault Equivalencies Single Stuck-At Faults Minimal Test Sets Example Test Set The Problem Combinatorial Circuit Formation Rules for the Existence Function Forming Links Selecting a Chain Advantages of the Test Sequence Simple Gates - Sequences Extension to Three-State and Bidirectional Structures Extension to Sequential Circuits Reference Case Study - 16:1 MUX D Flip/Flop Circuit 100% Fault-Grade Vector Set The Marquand Map 2;1 MUX Example 3:1 MUX Example 16:1 MUX Actual Test Vectors Chapter 10 Design Submission ASIC Glossary Glossary A-D Glossary E-K Glossary L-R Glossary S-Z Symbols	Faults and Fault Detection Last Edit July 22, 2001 Extension to Three-State and Bidirectional Structures Three-state and bidirectional structures, such as TTL three-state outputs and bidirectional I/O macros, may be tested using the Minimal Test Sequence. The states for which the Existence Function map shows a Z (for three-state) or a PAD (for bidirectional macro in input mode) are mapped along with the conventional points with a value of one. The EN enable is treated as any other input. The same link formation rules apply. The differences are: A link may exist with 1 or 0 at one end and Z or PAD at the other. There are no PAD-PAD or Z-Z links. A 1-Z, Z-1, 0-Z or Z-0 link does not violate the rule requiring that an output change state on each successive vector. Using the same basic rules as before with these additions, a Minimal Test Sequence was successfully developed for both a TTL three-state output and a bidirectional I/O macro. Extension to Sequential Circuits Sequential circuits are testable with the Minimal Test Sequence. The sequence is applied after the circuit is initialized. The Existence Function is developed mapping the Qn points representing "hold previous value". These are handled in the same manner as the Z or PAD values of the three-state and bidirectional devices. Violations of the rules requiring an observable output to change state occur when a 1-Qn or 0-Qn link is used. In fact, a sequential circuit must test HOLD 0 and HOLD 1. The sequence must include 1-Qn-1 and 0-QN-0 connections. A sequential device with a set or reset must be tested as shown in Table 9-6. Table 9-6 Sequential Device Start with the circuit showing an unknown X state on the output(s) Execute a SET or RESET to initialize the device Begin the sequence, starting from the SET or RESET state For a device with SET and no output inversion, the toggle X-1 is tested but the toggle X-0 is not. For a device with RESET and no output inversion, the toggle X-0 is tested but the toggle X-1 is not. Reference For reference, test sequences for SSI logic are listed on Advanced Logic Circuit Design Techniques, page 259 of Svoboda, White, Garland STPM Press, 1974. Simplistic invertors and non-inverting drivers are not listed. Several combinational circuits are examined in detail. They were chosen based on their characteristics and cover a range of difficult test situations. A three-state output, a bidirectional I/O, a latch and a D flip/flop macro are examined here.
Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc. For problems or questions on these pages, contact [email protected]