Logic Design for Array-Based Circuits
by Donnamaie E. White
Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc.
- Table of Contents
- Preface
- Overview
- Chapter 1 Introduction
- Chapter 2 Structured Design Methodology
- Chapter 3 Sizing the Design
- Chapter 3 Appendix = Case Study in Sizing a Design
- Chapter 4 Design Optimization
- Chapter 5 Timing Analysis for Arrays
- Chapter 6 External Set-up and Hold Times
- Chapter 7 Power Considerations
- Case Study: DC Power Computation
- Case Study: AC Power Computation
- Chapter 8 Simulation
- Case Study: Simulation
- Chapter 9 Faults and
Fault Detection
- Introduction
- Controllability
- Observability
- Masking a Fault
- Fault Types
- Fault Equivalencies
- Single Stuck-At Faults
- Minimal Test Sets
- Example Test Set
- The Problem
- Combinatorial Circuit
- Formation Rules for the Existence Function
- Forming Links
- Selecting a Chain
- Advantages of the Test Sequence
- Simple Gates - Sequences
- Extension to Three-State and Bidirectional Structures
- Extension to Sequential Circuits
- Reference
- Case Study - 16:1 MUX D Flip/Flop Circuit
- Chapter 10 Design Submission
- ASIC Glossary
Faults and Fault Detection
Last Edit July 22, 2001
Simple Gates - Sequences
The Existence Functions for the SSI gates NAND and NOR are shown in Figure 9-6. The Existence Functions for the SSI gates AND and OR are shown in Figure 9-7. In both figures, the gate, the logic equation it represents and a Marquand Map of the Existence Function is shown. Marquand maps date from the 1880's.
Figure 9.6 Simple SSI Gates: NAND, NOR
Figure 9.7 Simple SSI Gates: AND, OR
The logical distance 1 edges are also shown. The test sequence can start at any node, and traverses each link in both directions. The sequences for the AND and OR gates are shown in Figure 9-8. An analysis of the fault coverage for the AND gate sequence is shown in Figure 9-9.
Figure 9-8 AND, OR Gate Minimal Sequences
| Y1 | C B A | Y2 | C B A |
|---|---|---|---|
| 1 | 1 1 1 | 0 | 0 0 0 |
| 0 | 0 1 1 | 1 | 0 0 1 |
| 1 | 1 1 1 | 0 | 0 0 0 |
| 0 | 1 0 1 | 1 | 0 1 0 |
| 1 | 1 1 1 | 0 | 0 0 0 |
| 0 | 0 1 1 | 1 | 1 0 0 |
| 1 | 1 1 1 | 0 | 0 0 0 |
Figure 9.9 Sequence Analysis - AND Gate
| Y1 | C | B | A | FAULTS COVERED |
|---|---|---|---|---|
| 1 | 1 | 1 | 1 | Y1 SA0; A or B or C SA0 |
| 0 | 0 | 1 | 1 | C SA1; Y1 SA1 |
| 1 | 1 | 1 | 1 | Y1 SA0; A or B or C SA0 |
| 0 | 1 | 0 | 1 | B SA1; Y1 SA1 |
| 1 | 1 | 1 | 1 | Y1 SA0; A or B or C SA0 |
| 0 | 0 | 1 | 1 | A SA1; Y1 SA1 |
| 1 | 1 | 1 | 1 | Y1 SA0; A or B or C SA0 |
Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs
Enterprises, Inc.
For problems or questions on these pages, contact [email protected]