Logic Design for Array-Based Circuits

Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc.

• Table of Contents
  
• Preface
  
• Overview
  
• Chapter 1 Introduction
  
• Chapter 2 Structured Design Methodology
• Chapter 3 Sizing the Design
• Chapter 3 Appendix = Case Study in Sizing a Design
• Chapter 4 Design Optimization
• Chapter 5 Timing Analysis for Arrays
• Chapter 6 External Set-up and Hold Times
• Chapter 7 Power Considerations
• Case Study: DC Power Computation
• Case Study: AC Power Computation
• Chapter 8 Simulation
• Case Study: Simulation
• Chapter 9 Faults and Fault Detection
  • Introduction
  • Controllability
  • Observability
  • Masking a Fault
  • Fault Types
  • Fault Equivalencies
  • Single Stuck-At Faults
  • Minimal Test Sets
  • Example Test Set
  • The Problem
  • Combinatorial Circuit
  • Formation Rules for the Existence Function
  • Forming Links
  • Selecting a Chain
  • Advantages of the Test Sequence
  • Simple Gates - Sequences
  • Extension to Three-State and Bidirectional Structures
  • Extension to Sequential Circuits
  • Reference
• Case Study - 16:1 MUX D Flip/Flop Circuit
  • 100% Fault-Grade Vector Set
  • The Marquand Map
  • 2;1 MUX Example
  • 3:1 MUX Example
  • 16:1 MUX Actual Test Vectors
• Chapter 10 Design Submission
• ASIC Glossary
  • Glossary A-D
  • Glossary E-K
  • Glossary L-R
  • Glossary S-Z
  • Symbols

Faults and Fault Detection

Last Edit July 22, 2001

Fault Types

Faults may be indeterminate in value (suspended between logical 1 and logical 0), or determinate in value (exhibiting a 0 or a 1).

They may be transient (intermittent, time varying), in which case they are elusive and difficult to detect. Faults may be permanent, i.e., considered hard or solid, in which case they may be detected if they are not masked, i.e., are observable.

Multiple faults occur when more than one fault occurs at one time. The probability of multiple faults occurring in a circuit is relatively less than the probability of a single fault, but is increasing with the increase in circuit density. Single faults remain the most likely event.

Multiple faults can occur in such a manner that they can be degraded to an equivalent single fault. In this case, the input vectors that test for the occurrence of the single fault also test for the occurrence of the multiple fault condition.

Fault Equivalencies

There are several equivalencies that exist which are useful in fault detection and which make fault location potentially more difficult. Some of these equivalencies are shown in Table 9-2 and two cases are diagrammed in Figure 9-1.

Table 9-2 Fault Equivalencies

• One or more inputs to an OR gate stuck at 1 is equivalent to the output of the OR gate stuck at 1.
• One or more inputs to an AND gate stuck at 0 is equivalent to the output of the AND gate stuck at 0.
• All inputs to an OR gate stuck at 0 is equivalent to the output of the OR gate stuck at 0.
• All inputs to an AND gate stuck at 1 is equivalent to the output of the AND gate stuck at 1.
• Failure of at least one input and the output (multiple faulting) will result in the output fault being propagated, masking the input faults.
• Any gate output fault has, as equivalent, one or more single gate input faults (the inputs not necessarily inputs to that gate).
• Any gate input fault does not necessarily have an equivalent gate output fault.

Figure 9.1 Fault Equivalencies

Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc.
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