Logic Design for Array-Based Circuits

Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc.

• Table of Contents
  
• Preface
  
• Overview
  
• Chapter 1 Introduction
  
• Chapter 2 Structured Design Methodology
• Chapter 3 Sizing the Design
• Chapter 3 Appendix = Case Study in Sizing a Design
• Chapter 4 Design Optimization
• Chapter 5 Timing Analysis for Arrays
• Chapter 6 External Set-up and Hold Times
• Chapter 7 Power Considerations
• Case Study: DC Power Computation
• Case Study: AC Power Computation
• Chapter 8 Simulation
• Case Study: Simulation
• Chapter 9 Faults and Fault Detection
  • Introduction
  • Controllability
  • Observability
  • Masking a Fault
  • Fault Types
  • Fault Equivalencies
  • Single Stuck-At Faults
  • Minimal Test Sets
  • Example Test Set
  • The Problem
  • Combinatorial Circuit
  • Formation Rules for the Existence Function
  • Forming Links
  • Selecting a Chain
  • Advantages of the Test Sequence
  • Simple Gates - Sequences
  • Extension to Three-State and Bidirectional Structures
  • Extension to Sequential Circuits
  • Reference
• Case Study - 16:1 MUX D Flip/Flop Circuit
  • 100% Fault-Grade Vector Set
  • The Marquand Map
  • 2;1 MUX Example
  • 3:1 MUX Example
  • 16:1 MUX Actual Test Vectors
• Chapter 10 Design Submission
• ASIC Glossary
  • Glossary A-D
  • Glossary E-K
  • Glossary L-R
  • Glossary S-Z
  • Symbols

Faults and Fault Detection

Last Edit July 22, 2001

Formation Rules for the Existence Function

The inputs and outputs for a vector represent a point on the Existence function map that has a value of one. The set of all points of value equal to one is the Existence Function.

A Test Sequence is a sequence of tests or input vectors represented by a selected sequencing through the points of the Existence Function. A Minimal Test Sequence may not necessarily use all Existence Function points (minterms, vectors). The existence function for the sample circuit of Figure 9-2 is shown in Figure 9-3.

Figure 9.3 Sample Circuit (2-Stage NAND)

Forming Links

The points on the Existence Function, treated as minterms, are linked following the linkage rule:

Two points connect if and only if:

• The input variables are logical distance one
• A primary output variable toggles 0-1 or 1-0

Logical distance one for the input variables means that only one input variable may change state when traversing the link from one minterm to another. The primary output must be an observable output (as shown in Figure 9-4.)

The requirement that only one input change per vector is designed to reduce the instance of hazards and race conditions in the test vector set. Hazards are introduced during test when multiple inputs change state due to differences in the tester lead connections. The parametric vectors for the gate tree in the last chapter are written using the Minimal Test Sequence for the tree.

Figure 9-4 Adding The Logical-Distance-One Edges

Selecting a Chain

When all the possible links have been formed, there will be one or more observable chains or sets of links. The longest chain defines the desired Test Sequence.

Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White , WhitePubs Enterprises, Inc.
For problems or questions on these pages, contact [email protected]