Logic Design for Array-Based Circuits - D. E. White - eBook


Logic Design for Array-Based Circuits by Donnamaie E. White Copyright © 1996, 2001, 2002 Donnamaie E. White

Table of Contents Preface Overview Chapter 1 Introduction Chapter 2 Structured Design Methodology Chapter 3 Sizing the Design Chapter 3 Appendix = Case Study in Sizing a Design Chapter 4 Design Optimization Chapter 5 Timing Analysis for Arrays Chapter 6 External Set-up and Hold Times Chapter 7 Power Considerations Introduction Cell Types Define the Power Computation DC Power in a Bipolar Array DCPower in a BiCOMS Array Overhead Current DC Power in a CMOS Array TTL Outputs - CMOS Arrays ECL Static Output Power - All Arrays AC Power Worst-Case Power Adjustment Multiplier for DC Power Checking with the Vendor Power Reduction Techniques The Macros and Their Options Macro Option Examples Design Rules for Macro Options Power-Down and Conditional Geometry - Bipolar Terminated Outputs - Bipolar Terminated Outputs - BiCMOS, CMOS Inverted Outputs for Distotion Management Design Rules for Power Reduction (AMCC) Unused Inputs - Bipolar, BiCMOS MSI and High-Functionality Macros State Dependent Current - Bipolar Computing DC Power Dissipation Steps to Compute Maximum Worst-Case DC Power Reduction for Single-Supply Circuits CMOS and BiCMOS Arrays Design Rules when Power is to be estimated AC Macro Power Dissipation Case Study: DC Power Computation Case Study: AC Power Computation Chapter 8 Simulation Case Study: Simulation Chapter 9 Faults and Fault Detection Chapter 10 Design Submission ASIC Glossary Glossary A-D Glossary E-K Glossary L-R Glossary S-Z Symbols	Power Considerations Last Edit July 22, 2001 CMOS and BiCMOS Arrays BiCMOS arrays will simplify the computation since they will only compute DC power for the bipolar interface macros. Note that BiCMOS arrays still have an overhead current CMOS arrays emphasize AC power components and do not usually have DC components listed When Power is Specified Rather then Current Another variation in the computational method occurs when the macros are individually specified with a power dissipation, i.e., use this macro - dissipate this much power. The worst-case multiplier and the worst-case voltage may or may not be accounted for in the computation. Only addition is required to compute the macro power dissipation An overhead component for the bias circuitry may need to be computed and added to the macro sum. If typical power is specified, a worst-case multiplier or adjustment factor may be provided as previously discussed Design Rules when Power is to be Estimated Before trying to estimate power, verify that the specifications made for the macros are clearly understood Review the overhead (bias) current and how it is handled by the array Review the procedures specified by the particular array vendor for that array series since procedures may vary from series to series with the same vendor Review other vendor-identified power dissipaters - TTL IOEF, ECL static output AC Macro Power Dissipation To compute the AC power for any array, perform the computation shown earlier and repeated here: *PAC = 0.20 ( a * f * G )** where a is the power constant in microwatts/gate-MHz, f is the switching frequency G is the number of gates. There will be some variation in the form of the equation depending on the use of gates or macros or outputs as the sizing measure. There will be variation depending on the use of a register ratio and there will be variation in the types of macros for which AC power will be computed.
Copyright @ 2001, 2002 Donnamaie E. White, White Enterprises For problems or questions on these pages, contact donnamaie@sbcglobal.net