Logic Design for Array-Based Circuits
Copyright © 1996, 2001, 2002, 2008, 2016 Donnamaie E. White, WhitePubs Enterprises, Inc.
External Set-Up and Hold Times
Last Edit July 22, 2001
Overcoming Hold Time Error
Two options are available to overcome the problem of hold time error.
Figure 6-6 32-Bit Register: Two Clock Paths, Balanced Tree, Buffer Added
To compute the hold time of the design, the propagation delay of both paths needs to be determined while factoring in the effects of tracking. For the Q5000 Series, the effects are defined below.
For Like edges
Check with the vendor for the array to be used.
The buffer B1 in Figure 6-6 adds delay to the data path to prevent the hold time violation for th of macro FF16.
For unlike edges
Note: It is unlikely that two paths whose tracking in relation to each other is of concern, would be placed in different quadrants. If they are, consult with the array vendor.