Logic Design for Array-Based Circuits

• Table of Contents
  
• Preface
  
• Overview
  
• Chapter 1 Introduction
  
  • Introduction to Chapter 1
  • Design Tools [2001]
  • Design Options
  • Semi-Custom Arrays
    
  • Selection
  • Which Array Technology?
    • Size
  • Design Support Issues
    • Schematic Rules Checking
    • Reformatters
    • Design Upgrades
  • Exercises
  • Update 2000
• Chapter 2 Structured Design Methodology
• Chapter 3 Sizing the Design
• Chapter 3 Appendix = Case Study in Sizing a Design
• Chapter 4 Design Optimization
• Chapter 5 Timing Analysis for Arrays
• Chapter 6 External Set-up and Hold Times
• Chapter 7 Power Considerations
• Case Study: DC Power Computation
• Case Study: AC Power Computation
• Chapter 8 Simulation
• Case Study: Simulation
• Chapter 9 Faults and Fault Detection
• Chapter 10 Design Submission
• ASIC Glossary
  • Glossary A-D
  • Glossary E-K
  • Glossary L-R
  • Glossary S-Z
  • Symbols

Introduction

Design Options

The choices listed in Table 1-1 are available to the designer for whom off-the-shelf and bit-slice microprogrammable architectures are not good enough: full-custom arrays semi-custom arrays and simple-custom (gate) arrays.

Full Custom Arrays

If the bit-slice or off the shelf microprocessor solution is not adequate, the next option may be a customized design. Full customization for an application-specific design is not practical in individual components at the SSI/MSI level. Instead, one or more custom semiconductors can be designed that are specifically for and only for the application.

The customized VLSI chip may be totally designed by the customer - from the design of the components present in the individual cells (resistors, diodes, transistors, etc.) to the interconnect between these components in one cell and other cells.

All mask layers required to implement the full custom design must be generated specific to the application. Prototype and debug must encompass all layers. This approach will provide the smallest silicon and the most optimum solution if the designer is experienced. It can be the longest prototype time.

The key is the required expertise of the designer. The number of designers that can successfully design a fully customized array is significantly less than the designers that can successfully design an MSI/LSI PC board.

Depending on the manufacturer, a macro or standard cell library may exist that can speed the design time if the cells and macros are suitable for the application. The internal macro interconnects would still run through all mask layers. Design time may be reduced at the cost of some flexibility, but prototype time would remain lengthy. The advantage of the macro library is to help the designer by providing common functions while lessening the experience level required for a successful design.

Copyright © 1996, 2001, 2002, 2008 Donnamaie E. White , WhitePubs Enterprises, Inc.
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