Bit-Slice Design: Controllers and ALUs

Copyright © 1996, 2001, 2002, 2008 Donnamaie E. White

Preface

Table of Contents

1. Introduction

• Pre-Introduction
• Selection of the Implementation
• Microprogramming
• Advantages of LSI
• The 2900 Family
• Language Interrelationships
• Controller Design
• Constructing the CCU

2. Simple Controllers

• Sequential Execution
• Multiple Sequences
• Start Addresses
• Mapping PROM
• Unconditional Branch
• Conditional Branch
• Timing Considerations
• Pipelining
• Improved Architecture

3. Adding Programming Support to the Controller

• Expanded Testing
• Subroutines
• Nested Subroutines
• Stack Size
• Loops
• Am29811
• Am2909/11
  
• CASE Statement (Am29803A)
• Microprogram Memory

4. Refining the CCU

• Status Polling
• Interrupt Servicing
• Implementation - Interrupt Request Signals
• Vector Mapping PROM
• Next Address Control
• Am2910
• Am2910 Instructions
• JZ, CONT, JMAP
• CJP, CJV, LDCT, JRP, CJS
• JSRP, CRTN, RPCT, PUSH
• LOOP, CJPP, TWB
• Control Lines
• Interrupt Handling
• Am2914
• Interconnection of the Am2914

5. Evolution of the ALU

• Instruction Formats
• Control Unit Function
• PC and MAR
• Improving ALU Speed
• Adding Flexibility
• Am2901

6. The ALU and Basic Arithmetic

• Further Enhancements
• Instruction Fields
• Instruction Set Extensions
• Sample Operations
• Arithmetic -- General
• Multiplication with the Am2901
• Am2903 Multiply

7. Tying the System Together

• Expanded Memory for the Am2903
• MUX Requirements
• Status Register
• Am2904

Glossary

Last Edit September 23, 1996; July 7, 2001

Glossary

ACC

accumulator register

ALU

arithmetic logic unit

CC

condition code test input on Am2910

CCU

computer control unit -- contains ROM or PROM or WCS; the microsequencer; the IR; the pipeline (microinstruction) register; condition code MUX

Cf

minimum cycle width

Cp, CLK

clock signal (rising edge)

Cp

microcycle width; pulse width; clock signal time between two rising or active-signal edges

CPU

central processing unit

cycle time

when microprogramming, usually refers to one clock cycle; one microcycle or clock cycle being required to execute one microinstruction where a microinstruction is equivalent to a microstep

DIP

dual in-line pin package (other packages exist but are not as common for the bit-slice)

DMA

direct memory access

EPAC

electrically programmable analog circuit

EPROM

erasable PROM

EEPROM

firmware

program which controls the system,; usually stored in PROM/ROM memory but not restricted to read-only memory

FIS

fixed-instruction set

FPLA

field programmable logic array

Hex

hexadecimal

I/O

input/output

 

IP

Intellectual Property - used to refer to a pre-designed functional block that can be treated as a hard or soft macro

 

IR

instruction register

LIFO

last in; first out stack operation

LSB

least significant bit

LSI

large-scale integration (200-1000 gates per die); the name of a company

LSS

least significant slice (as in bit-slice)

macroinstruction

a machine-level instruction

MAR

memory (main memory) address register

microinstruction

an instruction that actually controls the hardware activity (binary bit-level)

microprocessor

one chip that contains control logic, registers and an ALU; the complexity of what is called a microprocessor has expanded beyond this primitive level

microprogrammable

the user may alter the control program

microprogrammed

the user may not alter the control program

microroutine

sufficient microinstructions to carry out one machine-level instruction

MOS

metal-oxide-silicon technology

MSB

most significant bit

MSI

medium-scale integration

MSS

most significant slice (in bit-slice)

MUX

multiplexor; a select-one-of-n device

opcode

operation code; part of a machine-level instruction which specifies the function to be performed

operand

data elements that will be operated on by the operation code

PC

program counter (main memory; machine programmed); more common definition is a personal computer

µPC

microprogrammed counter register; register which contains the address of the next microinstruction to be executed; more common definition is microprocessor

PCB; PC Board

printed circuit board

PLA

programmable logic array

PROM

programmable reads-only memory (user-programmed) [used in text to represent EPROMS and other variations of the basic PROM concept]

RALU

ALU with registers (scratchpad)

RAM

read-write memory (volatile)

ROM

read-only memory (factory programmed) (non-volatile)

RTL

resistor-transistor logic (original definition); register-transfer level (newer meaning)

scratchpad registers

local storage for user, system programs

SSI

small scale integration

I(ALU execution)

maximum delay of ALU from instruction lines stable to ALU output useable

t(counter clock to output)

maximum delay clock edge received by counter until output usable

ti (max)

worst-case maximum value of time ti

ti(min)

worst-case minimum value of time ti

t(pipeline click to output)

maximum delay clock edge received by pipeline register until output usable

t(PROM read access)

maximum time delay from address lines stable until PROM output stable

TOS

top of the stack

TTL

transistor-transistor logic

VLSI

very large scale integration such as ASICs (1000-100,000); the industry got a little crazy after this level and tried all sorts of acronyms to represent the really dense stuff

WCS

writeable control store; control memory built from read-write memory and therefore alterable (for microprogrammable systems)