Bit-Slice Design: Controllers and ALUs

The ALU and Basic Arithmetic

Last Edit November 1, 1996; May 1, 1999 ; July 15, 2001

Further Enhancements

If the Am2901 architecture is altered as follows then the design becomes that of the AMD Superslice™ RALU shown in Figure 6-1:

1. add connections and controls to allow for vertical expansion of the scratchpad registers

2. rearrange the Q shift and Q registers so that the ALU loads into the Q shift register directly
3. move the RAM shift to the ALU output
4. all data to be input on the ALU B port instead of the A port
5. allow data to be output from the B port of the scratchpad, which requires a tristate buffering of that port
6. allow data to be input directly into the scratchpad memory, bypassing the ALU
7. share the G' and P' pins with SIGN and OVR
8. enable the device to know if it the most, least, or middle significant digit, to allow arithmetic shifting
9. increase the possible functions which the ALU can perform

Figure 6-1 Am2903 RALU

Figure 6-2 Sixteen-bit RALU with carry-lookahead

The Am2903 is more powerful than the Am2901. It has a richer instruction set, including nine special functions which use user-inaccessible internal controls to facilitate operations such as two's complement multiply, sign extend, and normalization. It can be used with an expanded scratchpad memory so that the RALU is no longer limited to 16 registers. The ability to identify a slice as to its significance contributes to the instructional power available. The Am29203 will [it did] feature additional special instructions (BCD arithmetic).

Like the Am2900 family in general, the Am2903 is a low-power Schottky device with tristate outputs. The Am2903 is in a 48-pin package. The Am2903A and the Am29203 are ECL internal and TTL external for higher speeds. [Remember that this was the 1970s-1980s.]

Instruction Fields

The basic 9-bit instruction field is broken up into subfields differently from the Am2901:

• I_5-8 identify the destination, shifting, etc.,
• I_1-4 identify the ALU function, and
• I₀ is a MUX select.. I₀ normally appears with E'_A and OE'_B as a 3-bit source select control field.

Instruction Set Extensions

The basic arithmetic and logic function set of the Am2903 has several extensions to that of the Am2901, including all HIGH, all LOW and the logical NAND and NOR functions (Table 6-1).

Table 6-1 Am2903 ALU Functions

Shifting

There are two types of shifting possible owing to the identification of the significance of the slices. The logical shift shifts through all bit positions. The arithmetic shift shifts around the most significant bit position, i.e., the sign is undisturbed. The Am2903 data sheet provides a detailed table for the destination-shift control. Note that the source - ALU and destination control tables are valid only if:

For the case:

the special functions override the normal chip operations, with I_5-8 as the function select control field.

Three-Address Operation

The Am2903 may be used to perform a three-address operation. The given A-B addresses are used as the source addresses and a third address used as the destination. The second and third addresses are input to a MUX whose selection is under clock control such that the B address is stable for the read and the C address is stable for the write.

The third address must be in a register. The actual WRITE takes place on the rising edge of the clock. See the Am2903 data sheet for control details.