Bit-Slice Design: Controllers and ALUs

by Donnamaie E. White

Copyright © 1996, 2001, 2002, 2008 Donnamaie E. White

 
 

Preface

Table of Contents

1. Introduction

2. Simple Controllers

3. Adding Programming Support to the Controller

4. Refining the CCU

5. Evolution of the ALU

6. The ALU and Basic Arithmetic

7. Tying the System Together

Glossary

 

 

Refining the CCU

Last Edit November 2, 1996; May 1, 1999; July 7, 2001


Am2910 Instructions

Table 4-1 Am2910 Instructions

 

Instruction
Mnemonic
Behavior Binary Code
JZ Jump to Zero 0000
CJS Conditional jump to subroutine using pipeline register address 0001
JMAP Jump to Map (mapping PROM input) 0010
CJP Conditional jump to address in pipeline register 0011
PUSH PUSH stack; conditional load counter 0100
JSRP Conditional jump to subroutine from piepline register address
if tru, use pipeline address, if false, use register/counter address (continue)
0101
CJV Conditional jump to vector mappin PROM address 0110
JRP Conditional jump to register or pipeline 0111
RFCT Repeat loop stack address until counter not 0 1000
RPCT Repeat loop pipeline address until counter not 0 1001
CRTN Conditional Return 1010
CJPP Conditional jump to Subroutine and POP stack 1011
LDCT Load counter and continue 1100
LOOP Test for end of loop. If fails, repeat loop 1101
CONT Continue 1110
TWB Three-way branch 1111

Jump Zero (JZ)

Jump to Zero: Power-up or restart sequences need to use the Jump Zero instruction if the stack is to be used anywhere in the microprogram. JZ resets the TOS pointer to binary 0. JZ may be made to execute in various ways.

If a pipeline is being used, resetting the pipeline register to all zero sends 016 as the hex code for the instruction word. Since 016 = JZ (0000), the Am2910 executes JZ. A reset, restart or power-up control should cause the pipeline to reset.

Where the pipeline on the PROM memory does not exist, the OE' control on the Am2910 can be used with 10K pull-up resistors to force FFF16 on the address lines into the PROM memory. The JZ instruction should be placed at this location. This approach requires and extra microword in the memory, which is not usually a problem. Either of these appraoches is satisfactory.

JZ does not alter the register/counter, which is assumed to be undefined until reset. Any reference to the register/counter prior to a load instruction will result in unpredictable behavior.

The pipeline is left enabled in this instruction. With the exceptions of instructions JMAP and CJV, the pipeline is left enabled to improve execution speeds. A flow diagram for JZ is shown in Figure 4-9.

Figure 4-9 Jump zero (JZ, 0, 0000)

All instructions pass the next-address select bits, which include the Am2910 instruction field, the condition code multiplexer select bits, and any additional control pin fields (RLD', CCEN'). All instructions cause a next-address value to be switched through the next-address multiplexer and to be incremented by the incrementer.

Continue (CONT)

Sequential Execution: Sequentional program segments use the Continue statement, whose flow is shown in Figure 4-10. The µPC register is the source of the next-address. The register/counter and the stack are not altered. The CC' input is unused. The pipeline output enable PL' is enabled.

Figure 4-10 Continue (CONT, E, 1110)

Jump Map (JMAP)

Jump to the Map address: JMAP is trhe instruction used to start different microroutines based on opcode decode, and a mapping PROM or the equivalent construct. This GO TO branches to the address appearing at the Di inputs, and the MAP' output enable is active. In a CCU such as the one being discussed, this will gate the address output by the mapping PROM into the Am2910. The register/counter and stack are not affected. This statement is normally placed at the end of a microroutine or placed at a case-branch (jump-op) location in the microprogram (see Figure 4-11).

Figure 4-11 Jump map (JMAP, 2, 0010)

Figure 4-12 Sample Code for CONT, JMAP, JMP

Continue

 

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Copyright © September 1996, 1999, 2001, 2008 Donnamaie E. White WhitePubs Enterprises, Inc.