AMCC VINTAGE ARRAY INFORMATION - MAROMATRIX
AMCC discontinued its Array Business Unit January 1995. [ASIC - Application-Specific Integrated Circuit; not to be confused with today's arrays.]
However, as the chips age, people are trying to understand how they work so they can design a replacement. The seminar and the user manual did not contain any base-die (process) information. Everything discussed involved the two-layer metalization.
MacroMatrix was the custom software created by AMCC to handle the EWS workstations Daisy Logician, Mentor Graphics, and Valid. It handled support for customer-generated design submission checks, including ERCs and what we also call DRCs in today's EDA software tools.
Each workstation had its own Vol II of the Design Manual that went with the Vol I, which was specific to the particular array series.
Design Manual - Vol II - DAISY Logician User's Manual for the Q5000
Vol II Section 1 of the Q5000 - Daisy Logician User Manual (809) Introduction portion - MacroMatrix custom software in the design flow
Vol II Section 4 Simulation Rules and Guidelines (809) The simulations that must be run and submitted for a design - this version has DAZIX examples.
Vol II Section 5 Validation Guidelines (Checklist) (809) A summary of all those rules and checks that are still required today, and even today, not everything is automated. AMCC had a very sophisticated ERC rules-check that expanded every release. You can see some these early reports in Design Compiler and PrimeTime and other like products, and in the wafer-verification DRC checks. (See Synopsys.com for the software mentioned.)
Vol II Section 8 Introduction to MacroMatrix (809) MacroMatrix was the custom ERC and other submisson-checking software written at AMCC.
Appendix A MacroMatrix Software All the pieces as of (809)
Appendix B AMCCVRC Vector Rules Checking
Appendix C AMCCANN Annotation
Design Manual - Vol II - DAISY Logician User's Manual for the Q20000
Vol II EWS Schematic Rules (210) If you have never drawn blueprints, then you cannot understand how blueprints became schematics on a computer screen. They went up with the same rules, plus a few particular to the technology. These were $100,000 workstations, which boggles our minds these days.They ran simulations.They built netlists. Each one built their own! (Daisy, Mentor, Valid were the big three.) AMCC came up with translation program and had their OWN standard netlist. So did every foundry. Yikes!
Good to read over to see how Verilog and VHDL (RTL) came into being. How edif became a net-list standard. How the industry realized that every piece of software developed had to talk to other mainstream software and so-called 3rd party software. The switch to RTL and Design Compiler came in the 1990s.
By the time I joined Synopsys in 1997, Design Compiler was king, schematics were already a thing of the past (Design Analyzer will display them --- not good for big blocks of a design), everything was RTL (code), and even Synopsys used the Cadence Gate-Ensemble Place & Route software. Arrays went from Bipolar and BiCMOS to CMOS SOC, gate arrays, and now FPGA has taken over designs sized 4 Million gates and smaller. Blink. It will be different. But --- the basic design flow and all the "stuff" we used to do manually - is still there, in one form or another. The design flow never really changes. The tools come and go, but the steps never change.
Mentor EWS Operations (210) Each workstation had its own operations manual for running the AMCC MACROMATRIX package.
If you design today - you may not have a good overview of all the pieces or why we did what we did then, and you do what you do now. Having a good understanding of the physical design issues as well as the logical design issues makes a better designer. Most engineers today focus on only one part of the overall ASIC design flow or indeed, only one software tool (leading to early obsolescence). This seminar covers everything from Macro Selection to Wafer Fab.
A comment on macro selection: Design Compiler does a better job for you if you are intimately acquainted with the macro library you are to use. You can tell the synthesis tool that certain macros are NOT to be used, based on your knowledge of their cell size, power consumption, timing delays and drive. It makes the design reach objectives faster if you remove the "kids off the street".
The Bipolar designers faced tough design issues long before those same problems cropped up in the CMOS world. The BiCMOS, CMOS, and Bipolar arrays share approximately 85% of the same design rules. [Design Flow].
The seminar essentially covered the material in the above design manual. This version of the seminar (listed below) was for the Q3500 Bipolar array series, while the manual above is later, covering the Q20000 Bipolar array series.